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vanlandingham10
Observer
Observer
422 Views
Registered: ‎11-29-2017

DBI Enabled CL Cas Latency Value: vivado

Hello,

 

I am trying to figure out if I need to set my Cas Latency to 14 to account for Read DBI being enabled. When I hover over the setting window in vivado I get this response below.

"This field does not need to be modified when Read DBI is enabled."

However, when I look in the psu_init files I see that the cas Latency is set to CL is still set to 12 (CL for non-DBI) according to my Speed Bin. My question is this: 

Is vivado account for the CL in some other place in the code that checks to see if DBI is enabled before configuring the Mode Register bits for CL in the DDR device?

Does it hurt to just fix the CL in the configuration GUI in vivado to the value that accounts for DBI being enabled 14  instead of 12 in my case? I want to be sure the CAS Latency accounts for DBI. Thanks.

 

Running at 1600 (MT/s)  with -125 compatibility speed bin provided below.

 

vanlandingham10_0-1610731775200.png

 

 

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2 Replies
deepalir
Xilinx Employee
Xilinx Employee
329 Views
Registered: ‎02-21-2019

Hi @vanlandingham10 

Could you please share a screenshot of your DDR configuration. 

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vanlandingham10
Observer
Observer
323 Views
Registered: ‎11-29-2017

Well I found out that you can not make it Read CL  14 cycles in the gui with the mention of it saying its not needed when READ DBI is enabled. My question now is: 

If READ DBI is enabled and I cannot manually set the READ CL to 14 cycles, what does the .HDF tell the SDK to do to account for the extra latency required when READ DBI is enabled? Can you provide the bit settings I can check in the psu_init.c file or something.

vanlandingham10_0-1611180918946.png

 

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