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Registered: ‎02-02-2019

DDR Bus Arbitration: PS and HP0 want to access DDR at same

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we have customized Board by using Zynq 7045 FPGA-SoC, we have connected one DDR IC to this FPGA at its PS site. this DDR also can be access to PL side by using Master IP. if we want to do write to DDR from PS and Read from DDR to PL at a time, how can we arbitrate this DDR Bus  for its better operation.  Pl Read we want to give highest priority. once DDR PL Read request initiate then PS should relinquish the control on DDR Bus but PL transaction will over very short time after that again PS will take the control. that short time in which PL taken the control over the BUS what will happen to the PS data what he want to send  to DDR. what is the method to do this bus arbitration without loss  of data.

 

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demarco
Xilinx Employee
Xilinx Employee
386 Views
Registered: ‎10-04-2016

Hi jayakrushna@jetmail.ada.gov.in ,

If I am following your question correctly, this is your system:

1. Znyq-7000 with PS DDR

2. Two masters want to use DDR: the A9 processor and a PL master.

3. The A9 processor writes data to DDR.

4. The PL master reads data from DDR. It is not clear whether this is the same data the A9 has written.

Generally speaking, the multi-ported DDR controller has more bandwidth than any single master can generate. You typically do not need to worry about the relative scheduling of processor traffic versus PL master traffic.

Can you explain your bandwidth and latency requirements? Why do you think you are going to have problems in your system?

Regards,

Deanna

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demarco
Xilinx Employee
Xilinx Employee
387 Views
Registered: ‎10-04-2016

Hi jayakrushna@jetmail.ada.gov.in ,

If I am following your question correctly, this is your system:

1. Znyq-7000 with PS DDR

2. Two masters want to use DDR: the A9 processor and a PL master.

3. The A9 processor writes data to DDR.

4. The PL master reads data from DDR. It is not clear whether this is the same data the A9 has written.

Generally speaking, the multi-ported DDR controller has more bandwidth than any single master can generate. You typically do not need to worry about the relative scheduling of processor traffic versus PL master traffic.

Can you explain your bandwidth and latency requirements? Why do you think you are going to have problems in your system?

Regards,

Deanna

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