cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mjfox
Observer
Observer
8,525 Views
Registered: ‎08-11-2014

DDR Calibration Locks Microblaze

Jump to solution

Hello All,

 

We have a custom board using the Virtex 5 and DDR memory. We have simulated the MIG design with the memory model and nothing appears to break. However on the board the design does not calibrate. We are running at 125 Mhz.

 

We have attempted to run the provided mpmc_debug_v5calib_example.c program located in the MPMC SW folder for 14.7. The application will stall indefinitely on a memory write to the DDR. Memory reads fail as well.

 

We've also attempted to use the standalone XMD mwr and mrd commands. The mwr command stalls the processor at a memory access command.

 

Any help in the matter is appreciated.

 

Thanks,

 

Michael

0 Kudos
1 Solution

Accepted Solutions
mjfox
Observer
Observer
15,181 Views
Registered: ‎08-11-2014

Thanks for the reply! Yes, we have already gone through the debug guide. Unfortunately, everything checked off on the guide which is why we were so confused why the MIG wouldn't work.

 

Luckily, we've been able to get the DDR to initialize properly by assigning a static PHY and replacing the MIG. We've tested the entire memory range of the DDR using this PHY, and found they are all accessible and working.

View solution in original post

2 Replies
criley
Xilinx Employee
Xilinx Employee
8,506 Views
Registered: ‎08-16-2007

Have you already gone thru the Debug Guide in UG086? It's important that you adhere to all memory guidelines and board level requirements otherwise you may see calibration failures.

mjfox
Observer
Observer
15,182 Views
Registered: ‎08-11-2014

Thanks for the reply! Yes, we have already gone through the debug guide. Unfortunately, everything checked off on the guide which is why we were so confused why the MIG wouldn't work.

 

Luckily, we've been able to get the DDR to initialize properly by assigning a static PHY and replacing the MIG. We've tested the entire memory range of the DDR using this PHY, and found they are all accessible and working.

View solution in original post