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h4hussain
Adventurer
Adventurer
4,832 Views
Registered: ‎02-10-2010

DDR SdRAM write clocks

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hi

For DDR2 SDRAM controller write cycle how much clock are req to transfer 1 complete burst

 BL = 4

1st cycle address

2nd empty

3 data (0,1)

4 data (2,3)

 

total cycle = 4 with burest length = 4

 

if we are using BL = 8 , 6 clock will be used from the time the address is read to time the last data is read.

this is what MIG user guide is saying

 

What about if we are writing next burst

1st transfer BL=8 , clock used 6

concective 2nd write transfer BL=8 , clocks = ?

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jschmitz
Xilinx Employee
Xilinx Employee
5,245 Views
Registered: ‎10-23-2007

If you keep sending consecutive burst commands to the controller, then there will be no gaps in the data and you'll get a new burst of 8 every 4 clocks consecutively.

 

If you do not keep sending read commands to the S3 controller, then it will pre-charge the bank and your next read will have higher latency.

 

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jschmitz
Xilinx Employee
Xilinx Employee
5,246 Views
Registered: ‎10-23-2007

If you keep sending consecutive burst commands to the controller, then there will be no gaps in the data and you'll get a new burst of 8 every 4 clocks consecutively.

 

If you do not keep sending read commands to the S3 controller, then it will pre-charge the bank and your next read will have higher latency.

 

View solution in original post

h4hussain
Adventurer
Adventurer
4,807 Views
Registered: ‎02-10-2010

thanks

 

what about clk0_tb and rst0_tb

 

can I use it as main clk for my application

 

 

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h4hussain
Adventurer
Adventurer
4,784 Views
Registered: ‎02-10-2010

thanks

I have another question regarding read/write

 

By which (user applcation ) signal we can write APP_WDF_DATA to DDR2 and clear Read/Write FIFO

 

Thanks

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zc20060102
Visitor
Visitor
4,550 Views
Registered: ‎12-14-2009

when i apply  behavior sim to ddr sdram mig2.0,i found that dq wrongly triggered.

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