DDR address mapping

[Learn]

How address mapping is carried in ZCU102 DDR4 ,

Suppose the first address is 3347 & burst_len is 256 of increment burst type ,transmitting data of 128 bit ,

then next address = first address + burst_len  or first address + burst_len [16].

How exactly Mapping takes place from user address to what address at which data gets stored in external DDR4.

[zhangfeng]

Hello, @Learn .

Which DDR IP are you using?

[Learn]

Hello @zhangfeng .

Thanks for your reply.

Iam using DDR4 SDRAM IP.

[calebd]

@Learn 

@deepalir has a great post here on this topic: https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/How-to-map-the-AXI4-address-to-the-ddr4-memory-address/td-p/954407

Please look at that information and PG150 and if that doesn't answer your question, can you follow up with more info. on your question?

[Learn]

Thanks for the reply,

Iam transmitting data of 128 bit of burst size 64 , asize of 4 ( all 16 bytes of 128 bit is valid) for some number of burst ,after every burst complition I increment my address as

start address+ burst size(16) as Axi is byte addressing and when Iam reading the data for the address on which data is written I get the data as zeros.

[dgisselq]

@Learn ,

Let me see if I understand you correctly ... you are trying to do a transaction to memory, and the result isn't showing up?  You said the bus width was 64?  What were your transaction parameter?

AxSIZE=3'b011, AxBURST=2'b01, and AxLEN=8'h01 ?

Did you actually use AxADDR = 337?  If so, the first beat would've started at address 332, and the second at address 340.  Were your first WSTRB = 8'b1111_1111, the transaction would've been illegal.  The first WSTRB could be at most 8'b1110_0000.  Did you set WLAST to 0 on the first beat and to 1 on the second?  What BRESP did you get back?  Was it an error, due to attempting to access an invalid address?

All of these details matter when trying to figure out what happened.

Dan

[zhangfeng]

Hello, @Learn .

I thought you were confused about the relationships between AXI address, app_addr and DDR4 address,

but it seems that your question is only about AXI.

There is 4KB address boundary in AXI protocol, I recommend you to check if the burst transfer cross a 4KB address boundary.

[Learn]

Thanks for the reply,

Iam transmitting 128 bit i.e, 16 byte and burst Len is 64

64*16=1024, which is less than 4KB so iam not violating 

4KB address boundary

[dgisselq]

@zhangfeng ,

By that do you mean AxSIZE=3'b01 (16-bits at a time), and AxLEN = 8'd64?  This would generate a burst of 65 16'bit beats, not 64.  This would also require no more than 2'bits be set for any given WSTRB.

As for the 4kB boundary, whether or not you are crossing a boundary is not apparent from your response.  Basically, if the bottom 12 bits of your starting address are greater than (4kB - 65*2) 12'hf7e, then you will be violating protocol by crossing a 4kB boundary by issuing a read or write request given the parameters above.

Dan

[Learn]

Thanks for the reply,

My start address is 4096,iam transmitting 128bit awsize is 4, awlen is 63(burst Len is 64) wstrb is ffff, next address is 5120.

I have written the data and I got wlast signal also and when I read the data from address 4096 iam getting zeros

[zhangfeng]

Could you post the simulation waveform of DDR4 IP when using burst write/read ?

[Learn]

Thanks for the reply ,

Iam writing data ,@4096 as 37,38,39 ...such some random 64 data, i have written,as my burst Len is 64,when Iam reading the data from the address 4096 the ddr4_s_axi_rdata are 0.

[zhangfeng]

I have no idea why the read data is all 0.

In the IP catalog, you can click "Open IP example design..." to create a simulation environment for your DDR4 IP.

Did you compare the two  environments?

[Learn]

Thanks for the reply,

I had checked the open example design.

How this IP stores the written data at particular address how can I check that, so I can check that that read data.

This IP as instance  u_ddr_axi in which my read data is zero. 

[zhangfeng]

Have you confirmed the sucessful busrt write/read access in the simulation enviroment created by vivado?

[Learn]

After write burst iam getting bvalid signal, this is how I confirmed write burst.and read transaction confirmation is through read data only right.where my read data is 0.

[zhangfeng]

All the waves you have posted are captured from the example design?

Did you modify the example design?

If the example design is not modified, it should be ok, you can observe the successful burst write/read.

[Learn]

All the wave form I have posted are not example design.

I have a RTL code that generates the Axi signals which act as a master and gives that request to this IP to read or write from PL DDR.

[zhangfeng · Accepted solution]

The example design works well, so you should compare your own simulation enviroment with the example design to find why burst read is not working.

It seems that AXI is working properly, maybe the DDR4 model is not working properly.

Did you check the DDR4 model connected to the DDR4 IP you created?

[Learn]

Thanks for the reply,

First I thought IP itself creates a DDR model but in example design I saw they were using memory model , I used those model in the same way I was able to read the data.

Thanks zhangfeng .