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Visitor
Visitor
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Registered: ‎09-19-2018

DDR sysclk input circuit, UGs disagree

Hello,

I am looking at the sysclk input circuits as proposed by the MIS UG586, and SelectIO UG471. In my case, I have an LVDS clock going to the 1.35V DDR3 bank.

Figure A-1 of UG586 suggests 1K as a value for the bias divider, and the upper potential to be VCC1.2.
Figure 1-72 of UG471 and accompanying text suggests 10K-100K as resistor values, and the upper potential to be VCCO (which in this case is 1.35V).

The MIS UG586 does not mention the actual signaling standard for the clock in Appendix A, while UG471 specifically adresses the LVDS use case.

I think the difference is not that big, and I tend to follow the suggestion in UG471. Is there specific reasoning why UG586 would work better in that case, or should these recommendations be unified?

Regards,
fmueck

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Moderator
Moderator
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Registered: ‎11-09-2017

Hi @fmueck 

For DDR3 SDRAM interfaces that have the memory system input clock (sys_clk_p/sys_clk_n) placed on CCIO pins within one of the memory banks, the MIG tool assigns the DIFF_SSTL15 I/O standard (VCCO = 1.5V) to the CCIO pins. Because the same differential input receiver is used for both DIFF_SSTL15 and LVDS inputs, an LVDS clock source can be connected directly to the DIFF_SSTL15 CCIO pins.

Regards
Pratap

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Visitor
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Registered: ‎09-19-2018

Hi @rpr,

that's good to know, so for 1.5V, I can feed LVDS directly, if the common mode voltage allows that. Does that also apply to 1.35V in my case? If that's possible, why does the MIS UG recommend a specific circuit?

In my case, my clock source recommends/needs AC coupling, so I need to restore the bias using one of the proposed circuits. In this case (and in general), which one should I use?

Also, why are the circuits different?

Regards,
fmueck

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