I fail to simulation Post Translate DDR controller, I Use MIG 2.3 ISE 10.1.03 modelsim 6.3f
Trace the X ,I find the problem is IDDR ,When dq_delayed(It'Clk signal) is X ,the Q1 and Q2 is X,and this make read_data_rise signal is X Which is one of the mig_rd_data_0's port then at 242643850ps data_match_first_clk_rise(singal in mig_rd_data_0) become X then make so many Signal become X
Here is the only Warning I find in Modelsim: At time 206350.0 ps, WREN on X_FIFO16 instance sim_tb_top.u_mem_controller.\main_00/top_00/user_interface_00/backend_fifos_00/wr_data_fifo_160/Wdf_1 is high when RST is high. WREN should be low during reset. But I don't think It make DDR2 Controller failed.