08-30-2012 08:42 AM
I'm modifying an existing PCB design with no memory to incorporate a DDR2 memory controller. The design features an xc5vsx95tff1136-1 FPGA, and I'm designing in a Micron x16 data width DDR2 1 Gbit device. The components on this PCB are pretty expensive, so my priority is for this design to work first time. Cost, board size and component count considerations are secondary to risk (even though the latter are a factor).
I've cleared 2 banks on the FPGA and used the Memory Interface Generator version 3.61 to create a new design. I've allowed Mig to automatically assign the pins on the banks with nothing reserved, other than selecting DCI for DQ, DQS and Address/Control to reserve the VRP and VRN pins on each bank. I'm using a Texas Instruments tps51200 to generate the 1V8/0V9 reference voltages as this part works well on an existing Spartan6 DDR3 design. I'd like to ask for a few specific comments on some aspects of this design:
Digitally Controlled Impedance
I have put in 50 Ohm pullup resistors on the single direction signals, and 22 Ohm series resistors on the bidirectional signals. I've also connected up the ODT signal and put a 50 Ohm pullup on VRN and pulldown on VRP to match the impedance tracing we're using on the pcb. The plan is to initially produce the board with the 22 Ohm series resistors replaced by 0 Ohm parts and the DDR2 termination pullup resistors no-fit, and to use DCI on the FPGA and ODT on the DDR2 device to match the termination. If that doesn't work, then there will be pads to fit external biasing resistors as an insurance policy.
I notice that I require 2 differential clock signals to run the module. One is 200 MHz, and the other matched to the frequency I run the interface at (aiming for 266.67 MHz at the moment). Do these clock signals have to be external oscillators, or can I generate them internally using a second pll? I notice that the signals are in the example ucf pinouts and are explicitly named, and UG086 says they are routed through an IBUFG, so I think that I need two external oscillators which must match these frequencies.
Given that that's the case, can you point me to some requirements for the required ppm quality of these clocks? Can you suggest any 3.3V differential oscillators that have been previously used in such designs? I unsuccessfully tried sourcing a 200MHz differential clock some time ago for the Spartan6 design, and had to use a 125MHz part instead.
I can't find any guidance on decoupling Micron DDR2 devices. At the moment, I've just used a 100nF cap for every 2 voltage pins, and a 4u7 cap for the device. Does this sound reasonable?
Any sections of documentation that you could point me to would be greatly appreciated. I've had a look at some evaluation boards, but they mostly use DIMMS, or two Hynix devices, as in the ML523.
08-30-2012 08:59 AM
I'm using a Texas Instruments tps51200 to generate the 1V8/0V9 reference voltages as this part works well on an existing Spartan6 DDR3 design.
With a single DRAM, you can probably get by without a VTT suppy, using series termination rather than parallel termination. This might simplify your layout.
Have you reviewed the board layout guidance in UG086, chapter 14?
I can't find any guidance on decoupling Micron DDR2 devices.
I'm surprised that you could not find guidance in the Micron website. There are many examples of DDR2 devices used in development boards, readily available for download. In any case, the SP601 board uses a single DDR2 128Mx16 DRAM. Check page 5 of the SP601 schematics.
-- Bob Elkind
08-30-2012 09:42 AM
Thanks for such a swift reply Bob.
I've had a good read through the hardware design and layout sections of UG086. I looked through the datasheets for the DDR2 SDRAM on the Micron websites and searched the whole document for "decoupling", "bypass" etc and couldn't find anything. I also couldn't find anything in the many documents and technotes in their DDR2 Documentation and support section. Either way, it's good to see the example in the sp601. I was only looking at the Virtex5 evaluation boards and simply assumed all Spartan 6 boards would use DDR3.
Am I correct in my assumptions on the external oscillator requirements?
08-30-2012 10:15 AM - edited 08-30-2012 10:18 AM
The MIG-generated code is a complete "standard solution". MIG has a great deal of configurability, but its flexibility with respect to clock sources is limited. It is up to the designer to customise the clock sourcing and clock generation.
Many forum threads have discussed the customisation of clocking for MIG-generated designs.
I notice that I require 2 differential clock signals to run the module. One is 200 MHz, and the other matched to the frequency I run the interface at (aiming for 266.67 MHz at the moment). Do these clock signals have to be external oscillators, or can I generate them internally using a second pll?
You can use anything you like to arrive at the required result. I would reconfigure the PLL embedded in the MIG-generated code to use a 66MHz input clock from an external oscillator, and additionally configure the PLL to generate any 200MHz clock which is required for the idelay control logic. That is one possible example. Why would you need a second PLL?
If you aren't sure how to reconfigure the PLL, try using the CoreGen Clock Generator Wizard to provide the PLL configuration attributes which will generate the clocks needed in MIG (and in the fabric logic!) from the clock source and frequency of your choosing.
Given that that's the case, can you point me to some requirements for the required ppm quality of these clocks?
The requirements are rather loose, much looser than for USB or ethernet. Consult the datasheets for the DRAM (if the DRAM has an onboard PLL, it will have a requirement for input clock jitter) and for the Virtex-5 PLL. A crystal oscillator or [SiLabs or Maxim] silicon oscillator should be sufficient.
Can you suggest any 3.3V differential oscillators that have been previously used in such designs? I unsuccessfully tried sourcing a 200MHz differential clock some time ago for the Spartan6 design, and had to use a 125MHz part instead.
From UG190 (note the last line):
REFCLK - Reference Clock
The reference clock (REFCLK) provides a time reference to IDELAYCTRL to calibrate all IODELAY modules in the same region. This clock must be driven by a global clock buffer (BUFGCTRL). REFCLK must be FIDELAYCTRL_REF ± the specified ppm tolerance (IDELAYCTRL_REF_PRECISION) to guarantee a specified IODELAY resolution (TIDELAYRESOLUTION). REFCLK can be supplied directly from a user-supplied source, the PLL, or from the DCM, and must be routed on a global clock buffer.
Also see DS202, Table 64 for references to REFCLK.
-- Bob Elkind