UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
485 Views
Registered: ‎07-23-2009

DDR2 Spartan 6 Termination on address lines drain too much current after power up

Jump to solution

Dear all, 

I am experiencing a weird issue with one of our products which is based on a Spartan 6 XC6sLX75T FPGA and a micron DDR2 MT47H64M16 memory connected not via MIG but via MPMC (Multi-Port Memory Controller) in an XPC embedded design. 

The board has been developed in 2010-11 and has undergone some relayout, but the DDR2 part never needed any change. Lately we received a new lot of boards and some modules are defective because of a too high current drain on the 1.8V used to power FPGA and DDR2. The 1.8V converter is a MAX1556/7 configured to deliver up to 1.2 A @1.8V. On some boards, and on ambient temperature, when the card starts to get busy using in the DDR2 memory (the card uses also a PCIe endpoint from xilinx, this happens after a PCIe PERST deassertion) the 1.8V drops to half its value (0.9V) due to a current drain on the DDR2 memmory. (please look to the plot from power supply rails on fig.1)

even if not needed the engineer who designed the board put a 0.9Vtt termination converter (TPS51200) and termination of 50ohm on all address and control lines even if the micron guidelines suggest to avoid them of the lines are shorter than 2.5inches (our case, please see the schematinc in figure 2).

I verified that the overcurrent is drained from the 0.9VTT converter powering the 1.8V with an externa, more powerful power supply.. It appears that the terminations are draining more than 1.4 Ampere when the 1.8V is collapsing! since the termination resistors are 50ohm and they are 20 it is not physichally possible (360mA when all short circuited from 0.9V to ground) 

I checked and corrected the power up sequence of the DDR2 Vref which must follow the jedec standard (always as close as 0.3V from VDDQ/2 of the ddr) but I have seen no changes.

the Vtt termiantion voltage converter has been exchanged with a new one with no changes.

The weird things are:

  1. some boards are working fine
  2. some boards are failing but after get warmed ( from the 1.8 V converter getting hot) and rebooted they are working flawlessly even if the temperature is varying from -40 to +85°C (temp chamber)
  3. some boards are failing at ambient temperature but not at higher temperature

boards has been xrayed and we foud nothing, boards has been boundary scanned via JTAG and there is an issue when testing the address lines between the FPGA and the DDR2 (the one terminated), but everything works fine if we perform the boundary scan (interconnection test) with a few address line a time.

the only solution I found is to remove all 50 ohm termination resistors. In that case everything works fine (still have to verify the behaviour in the temperature range from -40 to +85°C).

I have found a solution but not the cause of the issue and since the termination resistors are on addresses and control lines which are outputs of the FPGA, I am assuming the FPGA (a -3I speedgrade) might be the problem. 

I am surely missing something, but what? Any help is appreciated!

thanks and best regards

 

 

fig 1.png
fig2.PNG
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Visitor jenze02
Visitor
475 Views
Registered: ‎07-12-2016

Re: DDR2 Spartan 6 Termination on address lines drain too much current after power up

Jump to solution

Dear Sir,

have you checked whether the TPS51200 might be oscillating in your high current situations? Not sure if this could be the issue, however, I came accross a similar situation some years back, which was caused by poorly decouling of the TPS51200.

Best regards

3 Replies
Highlighted
Visitor jenze02
Visitor
476 Views
Registered: ‎07-12-2016

Re: DDR2 Spartan 6 Termination on address lines drain too much current after power up

Jump to solution

Dear Sir,

have you checked whether the TPS51200 might be oscillating in your high current situations? Not sure if this could be the issue, however, I came accross a similar situation some years back, which was caused by poorly decouling of the TPS51200.

Best regards

Explorer
Explorer
469 Views
Registered: ‎07-23-2009

Re: DDR2 Spartan 6 Termination on address lines drain too much current after power up

Jump to solution
thanks for your hint.
The output voltage is stable on the tps51200 even when it drains a lot of current. I do not see it oscillating, but it gets very hot (FPGA and DDR2 are not hot at all under these circumstances). Surely the decoupling is a bit to less (we have 10uF instead of 30uf on outputs). On the TPS datasheet is written that the DDR2 devices may drain up to 1A during burst. our 1.8V converter cannot handle so much power, but it appears that the TPS51200 is the drain source.
that engineer 8 years ago made a very poor job.
0 Kudos
Explorer
Explorer
441 Views
Registered: ‎07-23-2009

Re: DDR2 Spartan 6 Termination on address lines drain too much current after power up

Jump to solution
You were right. Adding 30uF filtering capacitors to the termination voltage output VTT and 20uF to the VDDQ/VLDOIN input the issue was solved. I also tested a solution with only 20uF at output but is not reliable. With the new redesign we will remove completely (left un-populated) the VTT converter and termination resistor network because are not needed since the lines are shorter than 2.5 inches, but to solve the issue on the existing boards we will just remove all RTT termination 50 ohm resistors and leave the TIPS51200 populated but loadless. Thanks a lot, you deserve a KUDO and a solution!