03-27-2013 01:18 AM - edited 03-27-2013 01:54 AM
Hello every one,
Please answer my query to resolve the confusion. I will refere to the forumanswers here.
Fist of all same usual complain that ug406 looks make things little confused.
Any ways. I am confused about he BL-8 (or BC-4, but not conerned). My DDR3 is 16-bit DDR3 wide.
Hence its payload width is 16, right. Now according to this forum my burst length should be
(I am using Virtex-6 )
Now according to this message my burst length should be . 16*8 , right i.e. 128 bits, but since datawidth is 4*[PAYLOAD_WIDTH] hence 4*16 = 64 bits, so I have to transfer Two-data W0-W1 (according to write path eye-diagram) page 121 (figure 1-62).
I have following questions as well
1. Hence what increament of address should I do. I have to consecutively write data so for that should it be merely
app_add <= app_add + 1; -- note that orientation is (ROW-Bank-COL)
what if bank-row-col
or what... have no clue at all what so ever!!
2. Why is this burst length actually there at the first place, it seems like waste of (7 bits * datawidth ) per each data transfer. As far as I understand is that copy of the same data is copied to 8 locations. But then I came across this line in datasheet...
The burst lengthdetermines the maximum number of column locations that can be accessed for a given READ or WRITE command....
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A[i:2] when the burst length is set to 4 and by A[i:3] when the burst length is set to 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
after reading this I am thoroughly confused.
3. my data is 16 bit in itself. so should it be (a/c/ to figure 1-62 or 1-63 either)
W0 = d0 & d1 & d2 & d3 ; --where & denote concatenation and dx are the 16 bit datas; Wwidth = PAYLOAD*4 = 64bit
w1 = d4 & d5 & d6 & d7; --ofcourse this is just for here actual implementation is different in proper vhdl style.
Many thanks in advance
02-27-2014 02:56 AM
The memory devices will have a prefetch architecture and options to select the Burst length.
The burst length in short defines the number of write or read accesses to the memory device for a single write or read command.
Have a look at the below links and the data sheet of the DDR3 SDRAM you are using for more details.
02-27-2014 03:05 AM
To make it simple from my part, BL8 means Burst Length transfer of 8-data of width n, where n = width of data bus for DDR3 memory. So the addressing and data transfer with the BL8 transfer is that you generate address once with appropriate command (read or write) then respective 8 data transfer will happen.
When talking wrt to MIG from Xilinx, when you generate a single address the consecutive 8 locations will be having data transfer (read or write). Note that MIG offers the flat address space, which is broken into the respective banks, columns and rows and hence designer does not need to be in too much pain about that Bank,row, column thing.
Hope this helps