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gsemeraro
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Registered: ‎04-02-2020

DDR3 CAS Latency Setting

I am resurrecting an old design done by someone else where the DDR3 was never able to complete calibration.  I reviewed the DDR3 settings (MIG 3.92, mig_39_2b.vhd) and I found that the value for CAS Latency was set to 6 and the setting for CAS Write Latency was set to 5:

constant C3_MEM_CAS_LATENCY : integer := 6;

constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;

 

The datasheet for my memory (Alliance Memory, AS4C64M16D3A-12BCN) has a CL of 11 and a corresponding CWL of 8:

 

Speed Grade Clock Frequency CAS Latency t RCD (ns) t RP (ns)
DDR3-1600         800 MHz                11              13.75      13.75

CL=11, CWL=8

 

When I set C3_MEM_CAS_LATENCY  to 11 I get this error:

ERROR:Pack:2501 - Symbol
"Inst_BMD_EP_MEM/my_mcb_3port/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0" of type MCB has a property "MEM_CAS_LATENCY" with an illegal value of
"11".

Which makes sense because the documentation (Spartan-6 FPGA Memory Controller UG388 (v2.3) August 9, 2010) has this (page 21)

Memory CAS Latency   Possible values: 2, 3, 4, 5, 6, 7, 8, 9, 10

 

So, my question...does this mean that the DDR3 memory that is on the board is incompatible with the MIG 3.92 controller that I have?  Or is there some other way to determine the CL and CWL settings for this memory device other than from the memory device datasheet?

 

Thanks,
Greg

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4 Replies
gsemeraro
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Registered: ‎04-02-2020

The DDR3 datasheet supports 800MHz, I'm using only 200MHz clock so I divide (rounding up) the CL and CWL values by 4 meaning that I should set them to 11/4=3 and 8/4=2 respectively.  Alas, the memory datasheet only has specifications for CL from 5 to 13 and CWL from 5 to 9.  Not sure what is correct...  If there is someone with first-hand experience with this and they can confirm or deny my understanding I would appreciate it.

 

Thanks,

Greg

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gsemeraro
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Registered: ‎04-02-2020

The DDR3 is actually running at 333.33MHz so if my understanding of how the settings are calculated is correct (relative to 800MHz) I can use CL=5 and CWL=5 for my design which are valid settings for both the Xilinx controller and the memory device.  Again, if anyone with first-hand experience can confirm or deny this I would appreciate it.

 

Thanks,

Greg

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kren
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Registered: ‎08-21-2007

Did you update Vivado and get the calibration failure? Was any change on the hardware? You can open MIG wizard and check the suppored CL/CWL basing on your memory part and data rate it's running.

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gsemeraro
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Registered: ‎04-02-2020

Spartan-6, ISE

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