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lilia20190227
Observer
Observer
502 Views
Registered: ‎02-26-2019

DDR3,ECC

I'm looking to implement ECC with a design using DDR3.According to UG586,ECC is enable only for 72-bit. But the ddr3 memory which I use only has 16-bit width data bus. Is this contradict?

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rpr
Moderator
Moderator
477 Views
Registered: ‎11-09-2017

Hi @lilia20190227 

Xilinx MIG supports ECC over 72 bit width, doesn't support with 16 bit and  other bit width.

Regards
Pratap

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lilia20190227
Observer
Observer
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Registered: ‎02-26-2019

The ddr3 memory which I use only has 16-bit width data bus. And I shall implement ECC. What should I do in hardware?
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kshimizu
Xilinx Employee
Xilinx Employee
423 Views
Registered: ‎03-04-2018

Hello @lilia20190227 ,

 

It needs 72bits if you want to use the ECC.  It describes in the UG586, hence we can not provide how to use the ECC with 16bits.

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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ecc.PNG
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lilia20190227
Observer
Observer
405 Views
Registered: ‎02-26-2019

How I connect several 16-bit ddr3 memory in parallel to make 72-bit ?
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greatmaverick
Explorer
Explorer
369 Views
Registered: ‎04-06-2017

I have searched  Micron DDR3 products, no 72 bits DDR3 exists. 16 bits is the largest width. How can I use 72 bits DDR3?

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