I am using Vivado 2018.3, xc7k160tffg676-2, trying to use a DDR3 IP block.
I inherited this project, having been given a Xilinx archive zip file. When I unzipped the project would not build because files for the DDR3 IP were missing. Just attempting to regenerate the IP also failed, due to missing files, so I started from scratch to build a new block.
I was able to generate the IP block, almost identical to the module that had been instantiated. There is an issue with the 'reference clock', which the documentation suggests can be generated within the core but I couldn't find the control for that. So I let it add an extra pin.
After generating the core I could at least get the project to synthesize, but it failed implementation due to group conflicts on VCCAUX_IO. Okay, that would just be a mistake in specifying the core, I should be able to just re-customize the IP to fix it.
But when I click on the re-customize option I get an error: Filer to generate IP "ddr3". Failed to generate "Custom UI" outputs.
I searched the forums and there were other cases of this error and the workaround seemed to be to manually specify the pinout. But that is what I had done to start with, and I can't make any changes to the core because this error blocks me from doing anything.