05-17-2020 08:10 PM
Sorry that I am not able to sign up on digilent forum because of their website issues. The below link says, they suggested to used fixed pin-out for DDR3 interface mapping to FPGA pins. If anybody has link, for genesys2 Kintex7, Can you please share?
I used the option of letting tool do the mapping and it seems not working on FPGA.
The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up the process.
thank you in advance,
05-18-2020 05:13 AM
Few Eval boards XDC also available over github.com.
05-18-2020 05:42 AM
Hmmm. This XDC file contains many peripherals but NoT DDR itself.
Please let me know if I am missing something.
I used some file from other project . But ended up with DRC error of partially routed nets on 4 nets of ddr phy lanes. I have reduced DDR frequency by half that is clock period of 2500 ps, still same issue. The design was working fine with MIG 7series controller without axi interface . Now I needed axi based MIG controller. I followed digilent reference manual to configure MIG.
Do you have any suggestions , please ? I had worked in asic before but working on fpga for first time .