cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
raghavs
Visitor
Visitor
413 Views
Registered: ‎02-02-2019

DDR3 Interface Pin Mapping File for Digilent Genesys2 Kintex7 FPGA

Hi,

Sorry that I am not able to sign up on digilent forum because of their website issues. The below link says, they suggested to used fixed pin-out for DDR3 interface mapping to FPGA pins. If anybody has link, for genesys2 Kintex7, Can you please share?

I used the option of letting tool do the mapping and it seems not working on FPGA.

 

https://forum.digilentinc.com/topic/4035-genesys-2-board/

//////////

The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up the process.

/////

 

thank you in advance,

0 Kudos
2 Replies
rpr
Moderator
Moderator
375 Views
Registered: ‎11-09-2017

Hi @raghavs 

Few Eval boards XDC also available over github.com.

https://github.com/Digilent/Genesys2/tree/master/Resources/XDC

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
0 Kudos
raghavs
Visitor
Visitor
368 Views
Registered: ‎02-02-2019

Hi Pratap,

Thank you.

Hmmm. This XDC file contains many peripherals but NoT  DDR itself.
Please let me know if I am missing something.
I used some file from other project . But ended up with DRC error of partially routed nets on 4 nets of ddr phy lanes. I have reduced DDR frequency by half that is clock period of 2500 ps, still same issue. The design was working fine with MIG 7series controller without axi interface . Now I needed axi based MIG controller. I followed digilent reference manual to configure MIG.

Do you have any suggestions , please ? I had worked in asic before but working on fpga for first time .

Thanks,

Raghav

0 Kudos