01-01-2019 10:36 PM
i am using a zynq SOC xc7z020 1clg484i and i i have interfaced a DDR3 memory MT41J128M16 with Bank 502 of SOC. But now i want to use this DDR3 from PL side by using MIG.
Is it possible to use DDR3 from PL side by using MIG. Or it can only be accessed from PS side.?
I have tried using MIG but in the PIN selection tab bank 502 does not come in the drop down selection.
01-02-2019 09:32 AM
The PS memory controller that's assigned to Bank 502 can only be used by the PS memory controller because these are in the hardened ARM complex within the Zynq-7000 device. The MIG IP can only use the HP or HR bank pins available in the soft PL fabric. You can have IP in the PL fabric make accesses to the PS memory through the AXI memory map but that's totally different than trying to generate the MIG IP and trying to use the pins in Bank 502.
01-02-2019 05:48 PM
What is the name of the IP that i can use on PL side to make access to the PS side through the AXI interface and DDR3. OR do i have to write a code for that myself.?
01-03-2019 07:45 AM
Any AXI based IP that's placed in the PL can be connected to the PS AXI ports. UG585 talks about this concept on page 39 but I recommend going through the entire document and looking at some of the Zynq-7000 based eval boards and reference designs to get a better idea of how this works.
Here's a link to the latest version of UG585:
01-03-2019 05:51 PM
Can you point me to any example or a video tutorial.? Because this manual is difficult to understand and it will take a lot of time.
01-04-2019 09:35 AM - edited 01-04-2019 09:35 AM
I would take a look at the Xilinx Zynq-7000 eval kits like the ZC702 or ZC706, go through UG585, download some of the Zynq-7000 eval kit reference designs, open them up in IPI, and poke around a bit. I would also check out the Zynq UltraScale+ MPSoC ZCU102 or ZCU104 eval kits because they have nice IPI tutorials to give you a quick lesson in using the tools. You can see the IPI tutorials under the documentation tabs and then filter for Example Designs. XTP431 is for ZCU102 and XTP500 is for ZCU104.
01-21-2019 11:27 PM
I have a zynq 7020 board with DDR3 connected to its PS side. My application is to get an RGB888 image of 480x640 size with 90fps from camera and apply some image processing algorithms like crop and resize on it. I have already interfaced my camera with PL and started receiving frames. Now i want to transfer one frame from PL to PS and store in DDR3. And then read back the DDR3 from PL address by address so that i can crop and then resize image. I have tried the AXI interconnect and AXI DMA but i could not succeeded. Can you point me how to achieve that and which interfaces for communication between PL and PS will be easy to achieve my desired output.