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sheladiya_vijay
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Registered: ‎12-10-2012

DDR3 MIG Controller's Maximum Data Rate

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Hi,

 

I have generated MIG core for my DDR3 SODIMM module MT16JTF51264HZ-1G4 (supports upto 10.6 Giga Bytes/Sec, GBps). I'm using XC7K160T device and Vivado 2013.4 tool from Xilinx. 

 

I have generated the core as per my requirement and it does write and read perfectly fine. I have 20Gbps (Giga Bits per Sec) rated incomming data. The problem is, MIG is not able to handle this rate and doesn't assert app_rdy. So I want to know the maximum data rate that MIG can handle without any data loss.

 

I have tried my best to find the answer from ug586.pdf and many posts from Xilinx's Forum as well. But I couldn't get my answer satisfactorily. So can anybody please help in finding this?

 

Thanks & Regards,

Vijay

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vsrunga
Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Maximum data rate is just double that of your memory operating frequency multiplied by number of data bits.

But if you need maximum throughput then it depends on your traffic and many other MIG settings and memory part related timings.

 

Did you try below AR and its sublinks ? I think it should give you enough info.

http://www.xilinx.com/support/answers/41169.html

 

If in case you are not achieveing required throughput you can also go for native interface or phy only design and have your controller.

 

http://www.xilinx.com/support/answers/51204.html

 

Hope this helps

 

-Vanitha

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vsrunga
Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Maximum data rate is just double that of your memory operating frequency multiplied by number of data bits.

But if you need maximum throughput then it depends on your traffic and many other MIG settings and memory part related timings.

 

Did you try below AR and its sublinks ? I think it should give you enough info.

http://www.xilinx.com/support/answers/41169.html

 

If in case you are not achieveing required throughput you can also go for native interface or phy only design and have your controller.

 

http://www.xilinx.com/support/answers/51204.html

 

Hope this helps

 

-Vanitha

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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sheladiya_vijay
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Hi,

 

Thanks for your quick response...Vanitha.

 

I'm using MIG clock of 156.25MHz, 512bit data width, Write-Read-Write-Read type of traffic and this is my requirement. 

 

What would be the Peak Bandwidth here? Is it 10GBps?

 

Regards,

Vijay

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

I do not think 156.25Mhz and 512 bit data width are at physical interface  but can be UI data width and frequency

As said earlier max bandwidth depends on many factors so please go through the links that I pointed , run simulation for your sepcufic address pattern and do the calculation to know the value.

 

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sheladiya_vijay
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Hi,

 

Yes, this is at User Interface side, not at PHY. I want to know the Effective Bandwidth at User Interface side only.

 

Efficiency I can calculate as per 1st equation given at that link. But to calculate Effective Bandwidth I need Peak Bandwidth parameter in "Effective Bandwidth = Peak Bandwidth * Efficiency" equation, what value should I put there?

 

Regards,

Vijay

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Peak Bandwidth = 2* Memory opearting frequency*Memory DQ width

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rjsefton
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Registered: ‎11-25-2014

Hi Vijay -

 

The achievable memory bandwidth with SDRAM is very dependent on the usage pattern. There is a lot of overhead at the memory level if interleaving small read and write transactions to different areas of memory. You will achieve maximum throughput if you stream long bursts to/from consecutive memory addresses. I work with high-speed video cameras where we need every bit of memory throughput we can get and I make all transfers to/from memory 1k bytes (the maximum that our memory controller allows). With that usage pattern we're able to achieve about 95% of theoretical (peak) throughput.

 

Video is a special case where long contiguous transfers in and out of memory work well. Doing that may not be possible in other applications. But wherever you can, try to queue up data and make the memory accesses as large as possible.

 

Bob

 

 

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rjsefton
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Registered: ‎11-25-2014

I'll also add that looking at your interface with the memory controller in ChipScope will tell you a lot. You can see how much dead time occurs between memory access due to overhead at the memory level. Seeing that can help you tune your access patterns to maximize total throughput.

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sheladiya_vijay
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Registered: ‎12-10-2012

Hi Bob,

 

Thanks for sharing this valuable information...

 

Regards,

Vijay

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