09-02-2019 03:04 AM - edited 09-02-2019 03:05 AM
I am interfacing DDR3 with Spartan 6 in ISE 14.7 and i am having some issues in MIG core.
I have gone through UG388 and other docs. but i am little confused about the flow in which we should send data to ddr3 or vice versa.
- should we first fill the write FIFO and then give write command? What are the exact steps to write properly in memory with burst lenght 64?
-If i send more data than burst length or depth of FIFO then what will happen? Will first number of data gets neglected?
- If i give more data than FIFO size , does it write next data to it's next page? Does address gets incremented automatically to next page of memory?......(I'll be glad if i get detailed explanation about this)
-do we need to do all the process(wr,rd&command) after calibration signal goes high?..(that's what i am doing now)
09-02-2019 04:57 AM
The Xilinx MIG DDR3 includes an example_design of the IP core. The working(simulation) of this example_design is explained in the documentaion.
Did you generate the example_design and follow the simulation?
If not done, should be done first as it can answer many of your questions.
09-02-2019 11:21 PM
The write data should been written into the data FIFO before the write command written into the command FIFO.
When the FIFO full is asserted, the command/data FIFO will be accept the the new command/data.
You can get more infromation on the MCB operation at user interface in ug388 at: https://china.xilinx.com/support/documentation/user_guides/ug388.pdf .
09-04-2019 02:55 AM
Thanks for the help.
I did solve those problem.
MIG tool is not dual port tool, right? I mean if I want to perform dual port operation with this MIG tool where I can give different addresses for WR and RD then what should i do?
In here if change "cmd_byte_addr" then it will chnage for both rd and wr( I cannot continue from same address where i left, i have to give specific address again).