We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎10-09-2018

DDR3-MIG issue with Spartan 6


I am interfacing DDR3 with Spartan 6 in ISE 14.7 and i am having some issues in MIG core.

I have gone through UG388 and other docs. but i am little confused about the flow in which we should send data to ddr3 or vice versa.

- should we first fill the write FIFO and then give write command? What are the exact steps to write properly in memory with burst lenght 64?

-If i send more data than burst length or depth of FIFO then what will happen? Will first number of data gets neglected?

- If i give more data than FIFO size , does it write next data to it's next page? Does address gets incremented automatically to next page of memory?......(I'll be glad if i get detailed explanation about this) 

-do we need to do all the process(wr,rd&command) after calibration signal goes high?..(that's what i am doing now)



0 Kudos
3 Replies
Scholar dpaul24
Registered: ‎08-07-2014

Re: DDR3-MIG issue with Spartan 6


The Xilinx MIG DDR3 includes an example_design of the IP core. The working(simulation) of this example_design is explained in the documentaion.

Did you generate the example_design and follow the simulation?

If not done, should be done first as it can answer many of your questions.

FPGA enthusiast!
All PMs will be ignored
Xilinx Employee
Xilinx Employee
Registered: ‎08-21-2007

回复: DDR3-MIG issue with Spartan 6

The write data should been written into the data FIFO before the write command written into the command FIFO.

When the FIFO full is asserted, the command/data FIFO will be accept the the new command/data.

You can get more infromation on the MCB operation at user interface in ug388 at: https://china.xilinx.com/support/documentation/user_guides/ug388.pdf .

0 Kudos
Registered: ‎10-09-2018

回复: DDR3-MIG issue with Spartan 6

Hi @kren @dpaul24 ,

Thanks for the help.

I did solve those problem.

MIG tool is not dual port tool, right? I mean if I want to perform dual port operation with this MIG tool where I can give different addresses for WR and RD then what should i do?

In here if  change "cmd_byte_addr" then it will chnage for both rd and wr( I cannot continue from same address where i left, i have to give specific address again).

0 Kudos