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Visitor
Visitor
564 Views
Registered: ‎10-15-2018

DDR3 MIG problem

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Hello, I am building a project with Opal Kellys XEM7310 (Artix XC7A200T on board). And I need to implement a system with DRAM.

I don't want to use AXI4 interface, because I don't want any programming of the processor or anything like that. 

I would only need a simple interface like the one on the picture below. Input data is in the form of very simple FIFO (data, clk, wr_en) and then I would like to transfer this data to DRAM controller, calculating the address in between.

After the data is written to the DRAM, I would like to read it back in continuous a loop, and write to another FIFO, from which I would put this data to I/O ports.

The problem is that I cannot create the native interface (MIG), because I am working in block design and it only offers an AXI4 interface. But if I do it in IP integrator and instantiate it in VHDL file, it gives me errors. 

I am new to using Vivado and would really appreciate your help. Or maybe even some advice on how to do it with AXI4 interface, but without a processor.

Thank you very much,

Jernej

Zajeta slika.PNG

 

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Adventurer
Adventurer
428 Views
Registered: ‎05-07-2018

Hi

as @behnam_2705new  mentioned, You will not involved with AXI4 at all.

after you set MIG IP, generate an example design and you will see anything about AXI4 will be accomplished by Xilinx software for you.

then don't worry about AXI4.

good luck

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Explorer
Explorer
548 Views
Registered: ‎03-16-2019

I have instantiated IP integrator of MIG and I haven't seen an error about instantiation. (the project worked correctly)

I don't think that there is a difference between IP with AXI4 interface and those which haven't.

report an error in the forum than members can help you better.

 

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Xilinx Employee
Xilinx Employee
442 Views
Registered: ‎08-21-2007

If you don't want the AXI interface, I suggest you do not use block design and create MIG IP from IP catalog.

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Adventurer
Adventurer
429 Views
Registered: ‎05-07-2018

Hi

as @behnam_2705new  mentioned, You will not involved with AXI4 at all.

after you set MIG IP, generate an example design and you will see anything about AXI4 will be accomplished by Xilinx software for you.

then don't worry about AXI4.

good luck

View solution in original post

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Visitor
Visitor
382 Views
Registered: ‎10-15-2018

Thank you for your answers, I will try AXI4 interface :)

 

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