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sujoyetc
Visitor
Visitor
6,056 Views
Registered: ‎09-26-2015

DDR3 Memory interface problem on the ML605 board

Hi,

 

I am building an architecture on the ML605 board with the help of ISE 14.7. The architecture needs to talk to the DDR3 memory.

I generated the Xilinx "example design" using the IPcore Mig tool. However the problem is that the exam design does not work. 

I tried to analyze what is happening in the design by doing some analysis with the help of the 8 leds that are available on the board.

 

Here is my analysis (during the design creation I chose the clock to be single ended for the memory user interface in the mig tool).

example.v has an input clock clk_ref which is connected to LOC = "A10",  #Bank 34.

This clock goes to iodelay_ctrl.v where it generates anther clock "clk_ref_bufg" and an output signal "iodelay_ctrl_rdy signal".

I found that "clk_ref_bufg" does not toggle and "iodelay_ctrl_rdy signal" never goes high.

 

I think these might be the reason.

 

 

Please help.

 

NOTE:

1) I am attaching the ucf file that I obtained inside the example design folder.

2) I am compiling example_top.v 

3) How I loaded the project in ISE?

I went inside ../example_design/par/

There I executed the script file "create_ise.sh."

The script generated the ".xise" project, which I loaded in the ISE

 

 

 

 

 

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
6,011 Views
Registered: ‎07-11-2011

@sujoyetc

 

Can you open your synthesized design and check if clk_ref  is connected properly? 

Have you monitoted the clock on the board and is it 200Mhz clean clock? Have you checked if your design has come out of reset?

You can also use ILA or scope to confirm it.

Also run a quick simulation and check if iodelay_ctrl_rdy signal is asserted.

 

Hope this helps

 

-Vanitha

 

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