10-13-2020 02:33 AM
I'm newbie in fpga and get a trouble with mt MIG.
I have to bring-up a custom board with Artix-7 XC7A50TFGG484-2 and a single DDR3 chip (Micron MT41J128M16JT-125).
When I run hello world, it runs normally. But when I make a default memory tests project in SDK then run it. I have a trouble. It runs to first test (XIL_TESTMEM_INCREMENT), I write the incrementing value as the test value for memory. I only can write 83 (0x53) times to memory then the program hold on the number 84 of writing. I tried to write in other area of memory or changed value which was written to the memory and I got the same problem.
Then I change the testing range is first 50 bytes in DDR3, program can write successful to 50 bytes but when I read data from this 50 bytes, the program hold on at the first time reading data.
I check the PCB design, all pins are correct. All setting for MIG:
- Clock Period: 300ps - 333.33MHz
- Data Width: 16
- Input Clock Period: 6000ps - 166.667MHz
- System Reset Polarity: Active Low
- Output Driver Impedance Control: RZQ/6. RTT - On Die Termination: RZQ/6. (Rzq = 240 ohm)
- sys_clk_i: 166.667MHz, clk_ref_i: 200MHz
Micrblaze uses 100MHz clock.
I attached the hardware design in the below image. The second image is the line where program hold on ( I draw a red circle)( the default memory test in SDK).
What problem is it? What should I do to debug and find the raw reason to fix it?
Can someone help me? If you need more information, please tell me.
I found other case which has the same DDR3 and Artix-7 Parts (maybe it helps): https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/DDR3-memory-content-modified-or-read-write-error/td-p/857912
10-21-2020 10:05 AM
In that other thread, there are plenty of helpful responses that should lead you to your solution, but your case might be different so you will need to do experiments to understand what exactly this failure is coming from. In that other thread, it was an issue with incorrect Vref values which is a problematic issue with how the board was designed.
I would go through with great detail, our PCB guidelines to make sure none of those are missed. We also have further guidance for signal integrity within the US+ guide. I would take a look at both to give a better idea of how your board should be designed.
In addition, you could start taking measurements of your hardware to make sure there are no issues on the power, clocking, or reset lines, or on the DDR lines as well. I would take a look at a couple address bits, a data bit, and other Command/Address/Control bits. This guide should help you to do so adequately: https://www.xilinx.com/support/answers/62181.html
10-25-2020 08:08 PM - edited 10-25-2020 08:09 PM
I checked my hardware design and measure:
- The supply voltage for DDR is 1.35V, Vref is 0.675V.
- The Clock signal is normal. I try to test with the highest to lowest clock (measure the clock line to DDR too) but I got the same problem.
- The Reset Line: checked but I can't find any issue.
- The DDR lines: I removed the DDR3 IC and set all lines which connected with DDR3 to GPIO to check whethe they're normal. All the lines is good.
Thank you so much for the US+ information, I'll take a look at it.