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Registered: ‎11-27-2011

DDR3 Refresh Cycle Write Collision Problem

We are working with the ml605 evaluation board and interfacing with ddr3 memory using the MIG UI (BL8). Most of the time our design works fine, but when app_rdy goes low when app_en is asserted (due to the refresh cycle that happens every 200 clock cycles), the data being sent is stored in what appears to be a buffer and does not get written to the memory until the next write is sent. However, when the next write is sent, it's data is buffered and the previous data is written to memory.


We used the timing diagrams in UG406 and extended the app_en until app_rdy is high, but it did not solve the problem. What else could be causing this to occur?

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Xilinx Employee
Xilinx Employee
Registered: ‎08-16-2007

That sounds like a possible issue with the MIG controller that Xilinx Technical Support should look into. Please open a webcase on this for further assistance.

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