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Observer danbo.liang
Observer
5,689 Views
Registered: ‎03-20-2012

DDR3 can not work when generating reference clock using MMCM

Hi,

DDR3 need sys_clk(400MHz) and ref_clk(200MHz).

I generate sys_clk and ref_clk using MMCM whose reference clock is 200MHz, but DDR3 can not work(using example design).

Then, I still generate sys_clk using MMCM, but use the MMCM's reference clock as the ref_clk, as a result, DDR3 do work!

 

My questions:

1 sys_clk and ref_clk need phase align?

2 Why DDR3 not work when using ref_clk generated by MMCM?

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2 Replies
Observer danbo.liang
Observer
5,589 Views
Registered: ‎03-20-2012

Re: DDR3 can not work when generating reference clock using MMCM

up! up! up!
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Xilinx Employee
Xilinx Employee
5,559 Views
Registered: ‎07-11-2011

Re: DDR3 can not work when generating reference clock using MMCM

Hi,

 

sysclk and ref clk are independent.

refclk is used for idealy controllers and sysclock is the input of MMCM which will inturn derive all the clocks required for memory & controller opeartion.

 

When ref_clk is derived from MMCM , have you tied its lock signal  to reset ?

Are yo uable to see idelay_contrl ready signal asserted .

I think reset, input clock are the main thing to suspect here.

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