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Observer
Observer
658 Views
Registered: ‎09-07-2018

DDR3 controller placement error

I am trying to use the DDR3 SDRAM (MIG) IP for my HAPS system. I have imported the IP and followed the usual synthesis flow using Synopsys Protocompiler. It seems that when I reach the end that I have placement issues.

"ERROR: [Mig 66-99] Memory Core Error - [I_emul_v8_ddr3] Either port(s) c0_sys_clk_p, c0_sys_clk_n is/are not placed or un-supported clocking structure/circuit for memory ip instance. Please refer to clocking section of PG150 for supported clocking structures.
ERROR: [Mig 66-99] Memory Core Error - [I_emul_v8_ddr3] MIG Instance port(s) c0_ddr3_ck_n[0],c0_ddr3_ck_n[1],c0_ddr3_ck_p[0],c0_ddr3_ck_p[1],c0_ddr3_addr[0],c0_ddr3_addr[1],c0_ddr3_addr[2],c0_ddr3_addr[3],c0_ddr3_addr[4],c0_ddr3_addr[5],c0_ddr3_addr[6],c0_ddr3_addr[7],c0_ddr3_addr[8],c0_ddr3_addr[9],c0_ddr3_addr[10],c0_ddr3_addr[11],c0_ddr3_addr[12],c0_ddr3_addr[13],c0_ddr3_addr[14],c0_ddr3_addr[15],c0_ddr3_ba[0],c0_ddr3_ba[1],c0_sys_clk_n,c0_sys_clk_p,c0_ddr3_ba[2],c0_ddr3_cs_n[0],c0_ddr3_cs_n[1],c0_ddr3_cke[0],c0_ddr3_cke[1],c0_ddr3_odt[0],c0_ddr3_odt[1],c0_ddr3_reset_n,c0_ddr3_ras_n,c0_ddr3_cas_n,c0_ddr3_we_n,c0_ddr3_dqs_n[0],c0_ddr3_dqs_p[0],c0_ddr3_dm[0],c0_ddr3_dq[0],c0_ddr3_dq[1],c0_ddr3_dq[2],c0_ddr3_dq[3],c0_ddr3_dq[4],c0_ddr3_dq[5],c0_ddr3_dq[6],c0_ddr3_dq[7],c0_ddr3_dqs_n[2],c0_ddr3_dqs_p[2],c0_ddr3_dm[2],c0_ddr3_dq[16],c0_ddr3_dq[17],c0_ddr3_dq[18],c0_ddr3_dq[19],c0_ddr3_dq[20],c0_ddr3_dq[21],c0_ddr3_dq[22],c0_ddr3_dq[23],c0_ddr3_dqs_n[3],c0_ddr3_dqs_p[3],c0_ddr3_dm[3],c0_ddr3_dq[24],c0_ddr3_dq[25],c0_ddr3_dq[26],c0_ddr3_dq[27],c0_ddr3_dq[28],c0_ddr3_dq[29],c0_ddr3_dq[30],c0_ddr3_dq[31],c0_ddr3_dqs_n[4],c0_ddr3_dqs_p[4],c0_ddr3_dm[4],c0_ddr3_dq[32],c0_ddr3_dq[33],c0_ddr3_dq[34],c0_ddr3_dq[35],c0_ddr3_dq[36],c0_ddr3_dq[37],c0_ddr3_dq[38],c0_ddr3_dq[39],c0_ddr3_dqs_n[5],c0_ddr3_dqs_p[5],c0_ddr3_dm[5],c0_ddr3_dq[40],c0_ddr3_dq[41],c0_ddr3_dq[42],c0_ddr3_dq[43],c0_ddr3_dq[44],c0_ddr3_dq[45],c0_ddr3_dq[46],c0_ddr3_dq[47],c0_ddr3_dqs_n[6],c0_ddr3_dqs_p[6],c0_ddr3_dm[6],c0_ddr3_dq[48],c0_ddr3_dq[49],c0_ddr3_dq[50],c0_ddr3_dq[51],c0_ddr3_dq[52],c0_ddr3_dq[53],c0_ddr3_dq[54],c0_ddr3_dq[55],c0_ddr3_dqs_n[7],c0_ddr3_dqs_p[7],c0_ddr3_dm[7],c0_ddr3_dq[56],c0_ddr3_dq[57],c0_ddr3_dq[58],c0_ddr3_dq[59],c0_ddr3_dq[60],c0_ddr3_dq[61],c0_ddr3_dq[62],c0_ddr3_dq[63],c0_ddr3_dqs_n[1],c0_ddr3_dqs_p[1],c0_ddr3_dm[1],c0_ddr3_dq[8],c0_ddr3_dq[9],c0_ddr3_dq[10],c0_ddr3_dq[11],c0_ddr3_dq[12],c0_ddr3_dq[13],c0_ddr3_dq[14],c0_ddr3_dq[15] is/are not connected to top level instance of the design"

I have specified a location for all of these pins and made sure that the clock source is from the same bank I/O. I can see that the pin placements in my .xdc file that is used for P&R. My guess is that I am missing the step during implementation where I assign the memory ports using the "memory byte planner." But since my design flow does not involve using Vivado except to generate the bitstream. How can I manually place these memory ports.

I attached my .xdc file with all of the ddr3 pins placed. The extension was changed to .txt because I couldn't upload the file as .xdc.

I am confused why it teels me the the pins are not connectted to the top.

 

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Xilinx Employee
Xilinx Employee
560 Views
Registered: ‎08-21-2007

Are you using MIG for 7 Series? If so, please assign the pinouts within IP wizard according to your board layout.

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Observer
Observer
452 Views
Registered: ‎09-07-2018

This can be closed. The issue was with the Protocompiler optimizing the IP core during synthesis because of a poor IP import.

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