cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
10,126 Views
Registered: ‎03-02-2015

DDR3 debug by using the Example design

Jump to solution

Hi,

 

Continuation from thread: Read from DDR3 in user design.

 

I have a design which uses MIG to write & read from DDR3,while reading from DDR3 it is only issuing "000..000",so i wanted to debug using example design.

 

What is the flow ?

 

Do i select  the debug option in MIG,select the sample size & then open IP example design & then just generate the bit file

Is this it ?

 

By selecting the debug option in the MIG gui can i use it to debug my design or is it only for debugging example designs ?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
17,896 Views
Registered: ‎03-02-2015

Hi,

 

@vsrunga & @vemulad:

The link you've posted a solution which i've already been doing.This was the flow i was following - I edit MIG ip core to include debug option,select sample depth & then right click on ip core to open example design.

A new vivado project opens with example_top as the top module with a few VIO & ILA's instantiated but not generated.

 

I was thinking of maybe adding the required ILA & VIO from IP Catalog in example_design project but it looked like a lot of changes in gui,setting probe widths,so i stopped.

 

Tool : Vivado 2014.4

MIG Version : 2.3

View solution in original post

0 Kudos
6 Replies
Highlighted
Xilinx Employee
Xilinx Employee
10,122 Views
Registered: ‎02-06-2013

Hi

 

The example design will help to debug calibration or data issue using the traffic generator present in it.

 

If you want to debug your design then you need use the ILA cores and debug by inserting them in to your own design

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
10,117 Views
Registered: ‎07-11-2011

Hi,

 

The ILAs and VIOs that come with example design will be used for calibration debug but most of the signals can also be used to check if read data is correct at the phy, you can monitor mux_rd_rise0/1, mux_rd_fall0/1, rd_data_valid signals and see if expected data is avaliable

 

Otherwise you can instantiate another ILA for app_* signals, but that may not give you clear picture unless you go for board level debug.

If example design works fine and your own design do not I would sugget you to run simulation and check if expected results are obtained, then go for hardware testing

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Highlighted
Adventurer
Adventurer
10,105 Views
Registered: ‎03-02-2015

@yenigal:

 

Yes,i already have ila cores & a debug hub in my design.But was not able to read back data from DDR3,so while going through ug 586 doc i saw an option of setting debug in MIG GUI.

 

So,the debug option in MIG GUI is only for example design.

 

@vsrunga:

 

My design works fine at simulation level,so i will see using example design.But after generating example design i'm not able to see VIOs & ILAs files which should be coming with example design..I see a question mark on top of those file names.

Tags (2)
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
10,098 Views
Registered: ‎07-11-2011

Have you generated the example design from Vivado itself?

Please check similar discussion and see if it helps

http://forums.xilinx.com/t5/Design-Entry/7-Series-MIG-ILA-and-VIO-cores-not-generated/td-p/423939

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
10,097 Views
Registered: ‎09-20-2012

Hi,

 

Is this Vivado?

 

How are you opening example design? Are you using "open example design" option in right click menu to open the design?

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Highlighted
Adventurer
Adventurer
17,897 Views
Registered: ‎03-02-2015

Hi,

 

@vsrunga & @vemulad:

The link you've posted a solution which i've already been doing.This was the flow i was following - I edit MIG ip core to include debug option,select sample depth & then right click on ip core to open example design.

A new vivado project opens with example_top as the top module with a few VIO & ILA's instantiated but not generated.

 

I was thinking of maybe adding the required ILA & VIO from IP Catalog in example_design project but it looked like a lot of changes in gui,setting probe widths,so i stopped.

 

Tool : Vivado 2014.4

MIG Version : 2.3

View solution in original post

0 Kudos