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lionrouge
Adventurer
Adventurer
7,160 Views
Registered: ‎01-27-2014

DDR3 init_calib_complete doesn't go high in example design

Hi !

I have created a very simple project with DDR3 MIG core. It works - just doing simple write/read/check in an infinite loop.

But when i try to create an example design for the very same IP core i use in my design - it fails passing the calibration stage.
I know it for sure as i have routed init_calib_complete to one of the pins.
The same happens when i try to create a memory test app with Microblaze - init_calib_complete just is not asserted.

Could you please help me find out the issue?

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vemulad
Xilinx Employee
Xilinx Employee
7,155 Views
Registered: ‎09-20-2012

Hi @lionrouge

 

Is this failure seen in hardware?

 

 

Thanks,
Deepika.
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lionrouge
Adventurer
Adventurer
7,148 Views
Registered: ‎01-27-2014

How can i check it?
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lionrouge
Adventurer
Adventurer
6,149 Views
Registered: ‎01-27-2014

It's weird but our PCB works with settings as for Micron memory predefined in MIG.
I tried to change DDR3 between our PCB (we use Samsung) and KC705 (Micron) with different settings.
Everything works with Micron ( MT8JTF12864HZ-1G6 ) settings in the core. Both Samsung and Micron. On both boards.

So i think i need to ask another question: what could go wrong while creating custom memory part in MIG and why Samsung memory works with Micron timings.

P.S. The Samsung memory we use is dual-rank. And we have a problem with memory routing copied from KC705 (CK pairs in different byte groups). So trying to use Samsung memory as single rank. May it be the issue?

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vsrunga
Xilinx Employee
Xilinx Employee
6,144 Views
Registered: ‎07-11-2011

@lionrouge

 

I suspect if dual rank memory timings match with that of single rank. we do not genrally recommend that flow.

When you use dual rank as single rank how did you comminucate that to MIG?

Have you genearted the IP for single rank or dual rank? How is the extra cs tied on board?

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lionrouge
Adventurer
Adventurer
6,136 Views
Registered: ‎01-27-2014

I use Vivado 2015.2. It still doesn't have any way to explicitly point to MIG whether i use single or dual rank. When i create a custom part i just use some predefined part as the base. In my case i used KC705' Micron MT8JTF12864HZ-1G6 memory as a template. And it's single rank. So when i point Samsung' part bank/row/column width it creates a single rank memory with half of it's actual size (510MB instead of 1GB in my case).

Why do i do that? Because we copied our memory routing from KC705. And it's incompatible with MIG requirements for dual-rank memory - it has different CK pairs in different byte groups. I had a discussion here about that issue.

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