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Contributor
Contributor
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Registered: ‎05-11-2018

DDR3 interface on XC7A100TFGG676-1

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I am implementing a 48-bit 3 components (MT41K64M16XX-107) x16 DDR3 interface on the XC7ATFGG676-1 FPGA.

My system clock is 200 MHz.  My DDR3 clock is 400 MHZ (800Mbps) in a 4:1 Phy to Controller Clock Ratio.  This is the maximum clock rate for this FPGA.  The banks are HR so there is no DCI Cascading.

My current pinout has sys_clk_p by itself in bank 14.  Address/control are in bank 15 T0 & T1.  DQ[47:32] in bank 15 T2 & T3 and DQ[31:0] are in bank 16.

My intended schematic:

1. Will not have 0.75 V placed on the VREF pins since I am selecting internal VREF since my design is at 800 Mbps and lower (XC7ATFGG676-1 FPGA max DDR3 is 800 Mbps).

2. No 80.6 Ohm pullups/pulldown for VRP/VRN since these do not exist in HR banks.  Is this correct?

3. Trace Termination 50 Ohms.

4. VCCO 1.5 V

Key MIG selections with 800 Mbps: Are these correct or should they be changed?

output driver impedance control    RZQ/6

RTT(nominal) - ODT                     RZQ/6

Internal VREF selected since 800 Mbps

Internal Termination Impedance 50 Ohms.

System Clock               Differential

Reference Clock           Use System Clock

IO Power Reduction      ON

 

Additionally I am considering disabling data mask and tie the pins low on the board since we are not using them in our design.  This would free up pins to put the sys_clk_p/n and ddr3_reset_n in the Address/Control bank.  Is there any issue with doing this other than we can't use data mask later?

I have included the mig.prj file below as a reference.  I have also attached a spreadsheet with the ddr3 pin assignments for a more visual Am I missing something that was not mentioned above or in the mig.prj below?

Kerry

mig.prj

<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>ddr3_mig</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>ON</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>OFF</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7a100t-fgg676/-1</TargetFPGA>
<Version>4.1</Version>
<SystemClock>Differential</SystemClock>
<ReferenceClock>Use System Clock</ReferenceClock>
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>1</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41K64M16XX-107</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>48</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L17" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J14" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J16" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K15" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H19" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J19" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M17" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M16" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L15" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M15" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L14" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M14" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J15" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J20" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K20" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L18" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H18" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="K17" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="K16" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K21" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G21" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H14" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C17" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C22" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J24" SLEW="" name="ddr3_dm[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G24" SLEW="" name="ddr3_dm[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H15" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D16" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A19" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E17" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E18" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D18" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D19" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G17" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B22" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A22" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E21" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B25" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A25" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C26" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B26" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C24" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F17" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B24" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D23" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H21" SLEW="" name="ddr3_dq[32]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H22" SLEW="" name="ddr3_dq[33]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J23" SLEW="" name="ddr3_dq[34]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H23" SLEW="" name="ddr3_dq[35]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H24" SLEW="" name="ddr3_dq[36]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F23" SLEW="" name="ddr3_dq[37]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E23" SLEW="" name="ddr3_dq[38]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K22" SLEW="" name="ddr3_dq[39]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G15" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F24" SLEW="" name="ddr3_dq[40]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E25" SLEW="" name="ddr3_dq[41]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D25" SLEW="" name="ddr3_dq[42]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H26" SLEW="" name="ddr3_dq[43]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G26" SLEW="" name="ddr3_dq[44]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G25" SLEW="" name="ddr3_dq[45]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F25" SLEW="" name="ddr3_dq[46]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J25" SLEW="" name="ddr3_dq[47]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F15" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G19" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H16" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E16" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="F19" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A18" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A20" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A24" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="F22" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="D26" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="F18" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A17" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="B20" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A23" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="G22" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="E26" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J21" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J18" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="K23" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G20" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="M21/M22(CC_P/N)" Bank="14" name="sys_clk_p/n" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="35" trtp="7.5" tcke="5" trfc="110" trp="13.91" tras="34" trcd="13.91" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>NATIVE</PortInterface>
</Controller>

</Project>

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: DDR3 interface on XC7A100TFGG676-1

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It's seems ok and please considerate the termation for DDR3 address/control and data signals.

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Xilinx Employee
Xilinx Employee
597 Views
Registered: ‎08-21-2007

回复: DDR3 interface on XC7A100TFGG676-1

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It's seems ok and please considerate the termation for DDR3 address/control and data signals.

View solution in original post

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Contributor
Contributor
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Registered: ‎05-11-2018

回复: DDR3 interface on XC7A100TFGG676-1

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kren,

Can you explain what you mean by :

It's seems ok and please considerate the "termation for DDR3 address/control and data signals".

Kerry
 
 
 
 
 
 
 
 
 
 
 
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