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pgrangeray
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Registered: ‎05-31-2017

DDR3 memory content modified or read/write error

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Hi,

 

I'm back, with new trouble with mt MIG.

 

I have a custom board with Artix 7 XC7A50TFGG484-2 and a single DDR3 chip (Micron MT41K64M16-107).

 

After multiples troubles with PCB design, it seems to be good now.

DDR initialization is ok (init calib complete, app_rdy are high).

 

In the example design, tg_compare_error is asserted. Sometimes data are incorrect but this isn't most of time. 

 

I'm trying to write and read the DDR.

I write 68 times, in a single line, incrementing column by 8 (burst of 8, right?) (app_addr = 0, 8, 16, 24, 32 etc.), and each write I change app_wdf_data from "000....0000" to "FFF...FFF".

 

After that, i read the same address, and I suppose to read "000.....0000" "FFF....FFF" "00000...000" "FFF...FFF" but no!

 

MCU_reserved_3 is the app_read_valid signal.

 

I also tried by incrementing the value written. I can read it but some higher bits are modified (it's like random, but it's often the same bits, 103, 107, 91, 59 etc.).

 

I tried multiple writes followed by multiple reads, single write followed by multiple reads...

 

(app_wdf_mask is tied to 0, but i tried with "1" and it's the same. Strange!).

 

More read there is, more error there is...

 

I will post some screenshots for the incrementing value part, tomorrow.

 

If someone may help me! Thanks

write.png
read.png
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watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

Unfortunately, I found the route cause...

Please read the following to prevent like this issue. Keep in mind.

 

- Vref is very important to detect low or high for differential signals.

  In this case, there are CK, CK#, DQS and DQS#.

- If Vref is opened, at least DRAM chip can not correctly recognize low and high level.

  If a pair of CK and CK# and a pair of DQS and DQS# are ideal, it might work fine.

- If Vref is only opened at FPGA, you are luck. You might have a chance to adjust Vref.

  Would you investigate how to change Vref from external Vref to internal Vref and to adjust internal Vref ?

  I will investigate it. But I suggest it.

 

Let me know if you have any question.

I will reply it as soon as possible.

 

[Note]

Vref = 1/2 * VDD

So, in this case, typical Vref is 0.75[V] (DDR3) or 0.675[V] (DDR3L).

 

[Additional Information]

Would you refer the following AR #42036 ?

You can understand how to change/adjust VREF.

 

https://www.xilinx.com/support/answers/42036.html

 

Best regards,

 

View solution in original post

23 Replies
watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

I just confirm the followings to understand your situation more detail.

Would you reply them ?

 

- Did you analyze SI ?

- Did you make sure write and read access test with ex. PRBS7 pattern ?

- Did you make sure trace length on PCB ?

- Did you make sure a ripple voltage on each VCC ?

- How many layer did you use ?

 

I guess it seems trace length issue. But I don't have enough information to decide it.

 

Best regards,

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pgrangeray
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Registered: ‎05-31-2017

@watari

 

Thanks for your reply.

 

- What do you mean by SI ?

- PRBS7, I don't know this... Google says it's a pseudo random sequence. Why do you use it?

- Trace lengths are good. We corrected that.

- Ripple on each vcc : capacitor on each VCC, as requested. But i didn't scope it.

- For layers : board is composed by top, bottom and 7 internal layers (layer 4 is GND). FPGA and memory are on the top.

Address, bank, ras, cas, we, odt, reset, ck are on the bottom.

DQ, DQ and DM are on layer 5.

 

By watching screenshots I posted, I notice that for one app_addr, I assert app_en two times with different data. It is not what i wanted  to do...


Edit : So i correct it. Now, I write one at each address. It's better, but some bits are '1' whereas i write '0'. It's often the same bits (123, 107, 91, 59, etc.). How is it possible?!

 

I attach a table representing wrong bits. In red, bits (of app_read_data) that are always '1' (never goes low). In orange, bits that sometimes goes low. Others are good.

 

The first four bytes are bad. And for the others, only DQ11. Something wrong with the PCB?

 

And one more question : 

 

app_wdf_data is 128 bit wide in my case (for 16 bit DDR interface).

When i order a write command, how are placed the 8 words in the memory?

app_wdf_data[127:112] are at the first place, etc. or at the last (for BL8)?

Same for reading?

  

wrong bits.JPG
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watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

According to your result and explanation, I suspect the followings as route cause.

Would you make sure them ?

 

- Make sure trace length with DQS1/DQS1B from DQ8 to DQ15.

- Make sure VREF with cross point of differential signals.

 

Also, how do you define some parameter which are related to signal integlity ?

 

Best regards,

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pgrangeray
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Registered: ‎05-31-2017

@watari

 

So, how do you explain the errors on the first an second words (i don't know if MSB of app_wdf_data is send first or last), and not on the others (except DQ11)?

 

I will check at the office, and with an other board, maybe...

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watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

I suspect cross point issue from Hi-z to High or Low or mismatch of trace length, even though I don't get enough information from you.

 

Unfortunately, I don't have enough information to find the route cause and/or analyze more detail.

If you post measurement waveform by high speed osciiloscope, I can analyze more detail...

 

Best regards,

 

 

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pgrangeray
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Registered: ‎05-31-2017

@watari

 

Here is screenshot of port delay.

And here the track length on the board : 

  Length (mm)
DQ019,352
DQ119,395
DQ219,278
DQ319,582
DQ419,49
DQ519,895
DQ619,757
DQ719,594
DQ819,382
DQ919,658
DQ1019,988
DQ1119,114
DQ1219,988
DQ1319,44
DQ1419,669
DQ1519,947
DQS_p019,637
DQS_n019,654
DQS_p119,578
DQS_n119,432

 

The only scope i have is 100MHz max. Not enough i suppose?

 

 

trace0.JPG
trace_2.JPG
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watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

I see.

It's difficult to find out the route cause by this flow.

 

So, I have a plan to resolve this issue by a compromise plan.

Would you try it ?

 

- Change ODT value and DIC value by MRS at DRAM and confirm the result.

 

I guess you might be found fine result. If you found it, I suggest change the parameter.

If you didn't find it, unfortunately, I recommend to measure waveform by high speed oscilloscope to make sure overshoot, undershoot (all signals), skew (DQS vs 8bit DQs) and duty (DQS). (your oscilloscope (100MHz) is not suitable for this issue.)

 

Best regards,

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pgrangeray
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Registered: ‎05-31-2017

@watari

 

Thanks for your help.

 

I'm ok for your plan, but I don't know how to change DIC value?

And what value for ODT?

 

As you can see, i'm not a specialist in DDR... 

mig1.png
mig2.png
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watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

I mention to you.

Would you refer the followings ?

 

DIC => Output Driver Impedance Control

You can change amplitude of DQ from DRAM chip.

 

ODT => On Die Termination

You can change amplitude of output signals from FPGA.

Generally, user defines this parameter by result of signal integrity simulation.

However, in this case, there are not any result.So you should try six computational parameter.

 

Best regards,

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pgrangeray
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@watari

 

Ok, so if i understand your solution, i have to try all combinations with 2 values  for DIC (RZQ/7 and RZQ/6) and all 3 values for ODT (/6 /4 /2)?

 

Ok, i try it.

 

I also have the feeling that at the power up, there is less errors than after a lot of read/write cycles.

 

Thank you!

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watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

If you have any error during power up sequence and/or initial sequence, would you refer this post, too ?

 

https://forums.xilinx.com/t5/Memory-Interfaces/mig7-DDR3-dqsfound-not-working/m-p/858298#M12215

 

Best regards,

 

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pgrangeray
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@watari

 

During init, there isn't error, only tg_compare_error.

 

I tried the 6th combinations. 

The "best" are with DIC = RZQ/6 and ODT = RZQ/6 or RZQ/4. But first 16 bits (first word) are all "1"... Others words are good except bit 11. 

 

I will try reading thre times the same location, if something change or not.

 

New experiment : writing "000...000" "000...000" "000...000" "111...111" "111...111" "111...111" etc (3 times 0, 3 times FFFF).

During reading i get the first "000...000" wrong but the second and thirt good. Followed by "111...111".

So it's like some DQ are too slow to change between two write commands.

 

Sans titre.png
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watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

Um.

It's difficult to resolve this issue without schema, layout data and measurement waveform by high speed oscillator.

 

I guess you have the following problems.

Would you refer PCB guideline in MIG's document ?

 

- Cross talk issue

- Impedance mismatch

- Overshoot or undershoot issue by wrong  SI

 

BTW, if you change DRAM's clock frequency to low speed, how does it behavior ?

 

Best regards,

 

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pgrangeray
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@watari

 

I will post schematics, PCB layers design etc.

I think errors come from de Read. It's like a capacitor on DQ line that is too big and too long to discharge between '1' and '0'.

Read two time the same address gives almost the good value (DQ11 still high sometimes).

 

Track are design to be 40 ohm. Tracks length respect the rules (CK longer than others), bank and byte group are respected.

FPGA and RAM a placed very close, less than 1 cm between them.

 

It's the third time we design the board, and we've respected the rules (i hope).

 

For the frequency, actually period is 3200 ps, and the delta allowed by MIG generator is 2500 - 3300. I'm almost at the lower frequency. But i can try 3300 ps.

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watari
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Hi @pgrangeray

 

> I think errors come from de Read. It's like a capacitor on DQ line that is too big and too long to discharge between '1' and '0'.

 

If this is correct, you should rise slew rate of DQ signals from DRAM and reduce capacity component of trace pattern on PCB.

But I don't agree this hypothesis.

 

I suspect overshoot and/or undershoot by impedance mismatch by ex. wrong wire distance and/or through hole issue.

If the result is changed by different frequency, my hypothesis is probably correct.

However, I'd like to make sure waveform... It'S easy way to find the route cause...

 

Best regards,

 

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pgrangeray
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@watari

 

The closest layer (bottom) is a GND layer.

And the second closest (top) is a VCC layer (1.2V, 0.75V).

 

This is what i see with the scope for Vtt (0.75V) : 

Is it bad? It's not very continous...

 

DS0000.BMP
DS0001.BMP
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watari
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Hi @pgrangeray

 

Could you explain mode detail about two pictures ?

 

1) 1st picture is shown DQ11. Is it right ?

2) 2nd picture is shown Vtt or Vref. Is it right ?

 

If my understanding is correct, it's VREF or Vtt issue.

I suggest to make sure a circuit about VREF and Vtt or change Vref form external to internal and adjust Vref value.

 

If 2nd picture is shown expanded DQ11, unfortunately, your oscilloscope is not suitable to measure like this signal.

I can't suggest any more except to use high speed oscilloscope or to do SI with post layout design or pre layout design by ex. Hyperlynx.

 

Would you give me more information, if you need my help ?

 

Best regards,

 

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pgrangeray
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@watari

 

My apologies, it wasn't clear enough.

 

Two pictures are Vtt! 

First with a large timesclae, second with thin timescale.

 

I have difficulties capturing DQ, too many changes. But it is centered on 0.75V, with high level 1.5V and low level 0V (no picture).

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watari
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Hi @pgrangeray

 

Would you make sure the following ?

 

- Measure VREF. Like Vtt.

- Measure DQ11, DQS1 and Vref with a large timescale to confirm amplitude and level on same screenshot.

- Measure VDDQ

 

Best regards,

 

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pgrangeray
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@watari

 

Hum, on the package, the pins in blue called VREF must be connected to 1.5V or 1.35V?

 

Because in my design, there are not connected...

 

 

vcc.JPG
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watari
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Registered: ‎06-16-2013

Hi @pgrangeray

 

Unfortunately, I found the route cause...

Please read the following to prevent like this issue. Keep in mind.

 

- Vref is very important to detect low or high for differential signals.

  In this case, there are CK, CK#, DQS and DQS#.

- If Vref is opened, at least DRAM chip can not correctly recognize low and high level.

  If a pair of CK and CK# and a pair of DQS and DQS# are ideal, it might work fine.

- If Vref is only opened at FPGA, you are luck. You might have a chance to adjust Vref.

  Would you investigate how to change Vref from external Vref to internal Vref and to adjust internal Vref ?

  I will investigate it. But I suggest it.

 

Let me know if you have any question.

I will reply it as soon as possible.

 

[Note]

Vref = 1/2 * VDD

So, in this case, typical Vref is 0.75[V] (DDR3) or 0.675[V] (DDR3L).

 

[Additional Information]

Would you refer the following AR #42036 ?

You can understand how to change/adjust VREF.

 

https://www.xilinx.com/support/answers/42036.html

 

Best regards,

 

View solution in original post

pgrangeray
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@watari

 

I hope you are right!

 

On the RAM side, Vref is connected to 0.75V.

It's only on the FPGA side that Vref is not connected.

I try with Interval Vref and I come back (with good news i hope!).

 

Thank you @watari !

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pgrangeray
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@watari

 

 

Yes!!!!

 

You were right! The mistake was Vref not connected... So stupid...

Interal Vref saved me!

 

Thank you very much! :)