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Visitor
Visitor
4,013 Views
Registered: ‎07-18-2016

DDR3 placement and route error for artix 7

I am trying to run DDR3 (IS43TR16256A-125KBLI) on custom board with Xilinx Artix 7 200T FB676 on Xilinx ISE 14.5. I am able to generate MIG core successfully. I am using complete Bank35 same as Nexys video card but with different LOC names. nexys video pin schematic is shown in image.jpg

 

I wrote a top wrapper of MIG core XCO file, with simple logic of reset going high and low to check if calibration is done or not on board. Simulation, synthesize, translate, map all works fine with warnings. But PAR gets error, and error is

ERROR:Route:471 -

   This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be

   routed:

Unrouteable

Net:u_mig_core/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ctl_bus<0>

Unrouteable

Net:u_mig_core/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/tbyte_out

Unrouteable

Net:u_mig_core/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/tbyte_out

Unrouteable

Net:u_mig_core/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ctl_bus<2>

Unrouteable

Net:u_mig_core/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ctl_bus<7>

Unrouteable

Net:u_mig_core/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/in_rank<7>

Unrouteable

Net:u_mig_core/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/in_rank<6>

Unrouteable

Net:u_mig_core/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable

 

When I open FPGA editor and try to execute command route –all again same error generates.

How to resolve this problem same problem goes with Nexys video Kit. Attach is synthesis, translate, map, place and route reports with parameter setting.

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image.jpg
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8 Replies
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Xilinx Employee
Xilinx Employee
3,992 Views
Registered: ‎09-20-2012

Re: DDR3 placement and route error for artix 7

Hi @maheen_189

 

You need to regenerate the mig ip if you want to change any DDR3 pin locations.

 

You can use "verify pin changes and update design" flow in mig ip where you can source the mig .prj and updated .ucf files.

Thanks,
Deepika.
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Visitor
Visitor
3,990 Views
Registered: ‎07-18-2016

Re: DDR3 placement and route error for artix 7

I have already done that, issue is not pin locations. MIG verify pin changes gives all ok. problem is PAR error mentioned above

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Xilinx Employee
Xilinx Employee
3,988 Views
Registered: ‎09-20-2012

Re: DDR3 placement and route error for artix 7

Hi @maheen_189

 

You should generate the mig with new pinout and use the newly generated mig ip. Have you done that?

 

If you use old ip with new pinout you will run in to errors like this one.

 

Thanks,
Deepika.
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Visitor
Visitor
3,984 Views
Registered: ‎07-18-2016

Re: DDR3 placement and route error for artix 7

Yes i have done that with pin configuration as per "XC7A200TFBG676" Bank 35 pins. even i make clean project with these pins from very start.

Capture.JPG
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Visitor
Visitor
3,980 Views
Registered: ‎07-18-2016

Re: DDR3 placement and route error for artix 7

@vemulad All generation regeneration is done, but issue exist. I even try new project for Nexys video kit but issue is same. difference between custom board and Nexys video kit is: custom board FPGA is XC7A200TFBG676 while Nexys video kit FPGA is XC7A200TSBG484. means PIN LOC different. I created two different projects for both of them 

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Xilinx Employee
Xilinx Employee
3,965 Views
Registered: ‎09-20-2012

Re: DDR3 placement and route error for artix 7

Hi @maheen_189

 

Please share the below files

 

mig xco

mig prj

.ncd

Thanks,
Deepika.
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Visitor
Visitor
3,955 Views
Registered: ‎07-18-2016

Re: DDR3 placement and route error for artix 7

hey sorry for late reply. attached is complete project. can you find problem and resolve it and hen send it back to me.

thanks

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Visitor
Visitor
3,702 Views
Registered: ‎07-18-2016

Re: DDR3 placement and route error for artix 7

@vemulad no update ???? i am waiting for your response

 

 

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