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Newbie
Newbie
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Registered: ‎04-03-2019

DDR3 with ARTIX-7

Hello!

Artix-7 does not have external pins for connecting resistors to the MK and MKT ports. But there are built-in ones that are activated by the IP settings of the memory controller core in the FPGA (DCI mode), and the internal terminal resistors to the address and control signals will be turned on. In UG475 it is specified that ARTIX-7 has multifunctional ports, some of which can be used in VRP and VRN mode, the question is, how can they be transferred to VRP and VRN mode, so as not to use DCI mode and remain external terminal resistors?
Thanks!

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: DDR3 with ARTIX-7

When there's any IO pins configured as _DCI IO standard, the VRP/VRN should be connected according to UG471 and cannot be used as general IO anymore.

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