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Observer
Observer
1,026 Views
Registered: ‎07-10-2017

DDR3L to ZYNQ7000 interface

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Hi,

I am designing a DDR3L interface to ZYNQ7000  (on PS side) and in the process of flight time matching between the two.

I'm following the basic flight_time = sqrt(LC) equation to find the package pins internal delay on both FPGA and DDR3.

I assume I need to use the L & C values of ibis models of ZYNQ7000 FPGA and DDR3L and consider the internal delay of "both" for flight time calculation.

Reason asking is that I haven't seen in XIlinx forums any talk about considering the DDR3 side "package pins internal delay" and just talking about FPGA pins and PCB routing.

Appreciate your comments!

Thanks,

Reza

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Moderator
Moderator
949 Views
Registered: ‎11-28-2016

Hello @reza1,
Oh, my mistake.  You don't need to worry about the DDR3 package pin flight delays.  JEDEC defines all the timing at the BGA balls of the memory device.

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Moderator
Moderator
978 Views
Registered: ‎11-28-2016

Hello @reza1,

The package pin flight times as well as the IBIS models for the Zynq-7000 can be exported from within VIvado.  Once you have a post synthesis design you can issue a 'write_ibis' command to get the IBIS files. It will only include the pins and models that are actually used in your design so it's much simpler than using the generic IBIS model. UG933 talks about the memory interface routing guidelines.  Surprisingly the guidelines don't explicitly state that the package pin flight times need to be included while the existing 7-Series and UltraScale documentation does, but overall yes, absolutely, you need to include the package pin flight times.

You can either use the IBIS model information to generate the flight times or explicitly get the trace lengths.

To get the package pin trace lengths have your synthesized design open, go to the I/O Ports tab, right click anywhere in that part of the GUI, select Export I/O ports, and then select the CSV option.  It will give you the maximum and minimum pin trace lengths and you need to consider the average in your design.

Here's a link to the latest version of UG933:
http://www.xilinx.com/support/documentation/user_guides/ug933-Zynq-7000-PCB.pdf

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Observer
Observer
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Registered: ‎07-10-2017

Hi Ryana,

Yes, I already have exported the ibis model in Vivado for my project and have the internal flight times for the ZYNQ7000 pins, so no question about FPGA side.

My question is about the DDR3L memory that I use.

I have the ibis model for this micron DDR memory. Should i go ahead and run the SQRT(LC) for DDR3 pins to find the internal delay of DDR pins and consider them in my flight time/trace length matching as well? 

Is it like what shown below? Both FPGA and DDR3 should be considered when it comes to internal pins delays?

ZYNQ7000 (ibis) (find pins internal delay)  =====PCB_Trace=====DDR3L(ibis) (find pins internal delay)

Thanks,

Reza

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Moderator
Moderator
950 Views
Registered: ‎11-28-2016

Hello @reza1,
Oh, my mistake.  You don't need to worry about the DDR3 package pin flight delays.  JEDEC defines all the timing at the BGA balls of the memory device.

View solution in original post

Observer
Observer
926 Views
Registered: ‎07-10-2017
Hi Ryana,
Perfect! Thank you for the clarification!
Reza
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