1.Is it possible to generate a DDR3/4 48-bit interface MIG in Zync Ultrascale+ devices?
2.If yes, can you mention are there any restrictions with respect to the DDR Component part used?
3. How to verify DDR pin mapping correctness and timing in Vivado?
There are two memory interfaces for MPSOC, PS DDR interface - hard controller, and PL MIG interface - soft controller.
PS DDR effective data width is 32/64 - refer to UG1075 - Zynq UltraScale+ Device Package and Pinouts chapter 2
PL MIG supports to 48 bit data width- refer to PG150 - UltraScale Memory Product Guide
i would recommend you to check your requirement using vivado tool. Configure the core, validate, implement it and then you can generate the timing report.