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vangogh23
Visitor
Visitor
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Registered: ‎09-15-2020

DDR4/3 - 48bit Support in Xilinx Ultrascale MPSOC

1.Is it possible to generate a DDR3/4 48-bit interface MIG in Zync Ultrascale+ devices?

2.If yes, can you mention are there any restrictions with respect to the DDR Component part used?

3. How to verify DDR pin mapping correctness and timing in Vivado?

1 Reply
rpr
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Moderator
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Registered: ‎11-09-2017

Hi @vangogh23 

There are two memory interfaces for MPSOC, PS DDR interface - hard controller, and PL MIG interface - soft controller.

PS DDR effective data width is 32/64 - refer to UG1075 - Zynq UltraScale+ Device Package and Pinouts chapter 2

PL MIG supports to 48 bit data width- refer to PG150 - UltraScale Memory Product Guide

i would recommend you to check your requirement using vivado tool. Configure the core, validate, implement it and then you can generate the timing report.

Regards
Pratap

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