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ultrascaleaddict
Observer
Observer
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Registered: ‎11-08-2018

DDR4 Clamshell Topology and Write Leveling

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Hello,

Is write leveling also handled when having a clamshell topology or is it only available for fly-by architectures as mentioned in PG150 (DDR4 SDRAM feature summary page 12)?

I can't find any information regarding this feature for clamshell.

Thanks in advance for any hint.

Regards,

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rpr
Moderator
Moderator
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Registered: ‎11-09-2017

Hi @ultrascaleaddict 

Fly by and Clamshell are routing topologies, irrespective of routing topologies i.e., even if there is single DQS and DQ byte group then also the write leveling exist.

Regards
Pratap

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kren
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Moderator
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Registered: ‎08-21-2007

The write leveling is handled in both fly-by and clamshell topology.

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ultrascaleaddict
Observer
Observer
559 Views
Registered: ‎11-08-2018

Hello and thanks for the answer.

 

Is it mentioned somewhere? In some document ou application note for instance

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rpr
Moderator
Moderator
552 Views
Registered: ‎11-09-2017

Hi @ultrascaleaddict 

Fly by and Clamshell are routing topologies, irrespective of routing topologies i.e., even if there is single DQS and DQ byte group then also the write leveling exist.

Regards
Pratap

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View solution in original post

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