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Participant walidhendrix
Participant
379 Views
Registered: ‎07-10-2017

DDR4 Clock sharing

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Hello to everyone,

So I am targeting a KU060 and I need to use one differential system clock for both MIGs.

- I am using Vivado 2018.3

- I have a block design including a MIG instance (with teh famous "No Buffer" option selected)

- The block design is instantiated twice, one for each memory group

- System clock is on bank 44

- Memory group 1 is on banks 44, 45 and 46

- Memory group 2 is on banks 66, 67 and 68

- The clock path is : GCIO -> IBUFDS -> BUFG -> each MIG instantiation (I also tried the IBUFDS output for Group 1 and BUFG output for Group 2 but with no success).

- The BACKBONE constraint is in my xdc file:

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1}]

- I keep having the same error (see attached image)

Thank you in advance for any hint.

Regards,

 

Tags (4)
migClocks.png
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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
245 Views
Registered: ‎08-21-2007

Re: DDR4 Clock sharing

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As the two DDR4 controllers are not in the same column, it's sugggested to use separaterd system clock input in each column.

View solution in original post

4 Replies
Explorer
Explorer
314 Views
Registered: ‎03-16-2019

Re: DDR4 Clock sharing

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first of all, test your block design one by one. comment the other one and test DDR MIG on board. you will find your problem in a better way, as it seems from your error you will not pass the test in one by one test scenario. 

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Participant walidhendrix
Participant
304 Views
Registered: ‎07-10-2017

Re: DDR4 Clock sharing

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OK, so I tested the design one by one (even thoug I was sure about the result) and it gave what I expected:

- No problems when using the block dersign with the memory group 1

- Error with the memory group 2 (since not on the same column as the system clock)

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Explorer
Explorer
248 Views
Registered: ‎03-16-2019

Re: DDR4 Clock sharing

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your DDR clock must be placed on any GCIO pin pair in the same column as that of the memory interface. If you want to share the system clock input between two memory interfaces then both of the memory interfaces should be in the same IO column and in the same SLR.

 

 

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Xilinx Employee
Xilinx Employee
246 Views
Registered: ‎08-21-2007

Re: DDR4 Clock sharing

Jump to solution

As the two DDR4 controllers are not in the same column, it's sugggested to use separaterd system clock input in each column.

View solution in original post