01-23-2019 07:30 AM
Looking at AR# 71209 represents two types of DDR4 component for PL side of the UltraScale+ devices, i.e., x8 and x16. Also, looking at page 33 of ZCU106 User Guide indicates that the Xilinx has used x16 topology to configure DDR4 component of the PL side.
I have two questions :
1. Is there any specific reason that Xilinx has chosen x16 topology? Is there restriction that forces using this configuration?
2. What does Bank group in AR# 71209 stand for?
Thanks in advance for your kind replies and helps.
01-29-2019 09:41 AM
With x16 memory devices you get double the data width in the footprint of a single memory device. Meaning you'll have twice as much theoretical max bandwidth while using the same physical footprint when compared to x8 memory devices. The specific issue for AR#71209 is for the Zynq Video Codecs and how the PL MIG is not optimized to handle the traffic patterns generated by the video codecs.
As for the Banks and Bank Groups this is talking about the DDR4 memory device architecture and addressing. I recommend taking a look at a Micron DDR4 data sheet to get a better understanding of what this means. The key takeaway is that x4 and x8 DDR4 devices have 2 Bank Address bits and 2 Bank Group bits, which means you have a total of 4 Bank Addresses in each Bank Group for a total of 16 addressable Banks. For x16 deices you have 2 Bank Address bits and 1 Bank Group bit which means you only have 8 addressable banks. This gets in to DDR4 protocol, efficiently scheduling commands, how this relates to the command schedulers in the PL DDR4 controller, and with the specific video codec applications in the Zynq the MIG cannot meet the bandwidth requirements with x16 devices. If x8 devices were used then there would be better efficiency and the PL DDR4 controller could meet the bandwidth requirements.