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Observer
Observer
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Registered: ‎01-10-2013

DDR4 DIMM w/ ECC DQs to DQ Skew

Hi all, 

We're currently going over PCB constraints for DDR4 designs.

Previously for SODIMM we used to keep to UG583 and implemented skew constraints (+-10ps) within the whole byte. However this time we're dealing with ECC DDR4 DIMM, which brings another DQS to the byte. Given that DQS is now associated with a nibble, does this mean that skew constraints have to applied similarly ? 

Tl:dr -  Is it possible to apply skew rules to DQ nibbles and their associated DQS rather than the whole byte (2x DQS and 8x data lines) ?

Thanks in advance 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: DDR4 DIMM w/ ECC DQs to DQ Skew

Yes, the DQ and DQS associated with ECC (exrta byte) should be applied the same skew constraint.

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Observer
Observer
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Registered: ‎01-10-2013

回复: DDR4 DIMM w/ ECC DQs to DQ Skew

Dear Kren,

Thanks for your quick reply. However I don't think my question was properly understood. 
I wasn't referring to the extra byte, I was referring to length matching for a nibble rather than the whole byte. 

The image attached might help. Which one would be correct....option 1 or 2?

Untitled.png
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