02-10-2020 04:48 PM
We're currently going over PCB constraints for DDR4 designs.
Previously for SODIMM we used to keep to UG583 and implemented skew constraints (+-10ps) within the whole byte. However this time we're dealing with ECC DDR4 DIMM, which brings another DQS to the byte. Given that DQS is now associated with a nibble, does this mean that skew constraints have to applied similarly ?
Tl:dr - Is it possible to apply skew rules to DQ nibbles and their associated DQS rather than the whole byte (2x DQS and 8x data lines) ?
Thanks in advance
02-17-2020 03:10 PM
Thanks for your quick reply. However I don't think my question was properly understood.
I wasn't referring to the extra byte, I was referring to length matching for a nibble rather than the whole byte.
The image attached might help. Which one would be correct....option 1 or 2?