05-28-2020 12:21 AM
I have DDR4 interface requirement for custom RDIMM with 64bit interface(i.e without ECC). For RDIMM DDR4 memory option ECC is enabled by default. In user guide AXI control interlace have provision to disable ECC.
Please can anyone provide inputs will MIG work for 72 bit configuration and 64 bit physical memory connected and When should i disable ECC register(64-bit or 72-bit RDIMM connected) through AXI control interface (after/before controller reset release, calibration done or any other stage)
06-02-2020 03:19 AM
Controller provides an option to on/off ECC but when core configured to 72 bit then calibration logic try to calibrate 72 bit interface.
06-02-2020 05:21 AM - edited 06-02-2020 05:24 AM
Thank you for input. I have following observation after simulation If i modified simulation top to change memory model from 72 to 64 bit.
Scenario 1. 72 bit MIG AXI interface with ECC enable
Observation - Simulation fails with read error response. Data receive at application(AXI) interface is correct
scenario 2. 72 bit native interface with ECC disable
Observation - Application interface Data mismatch for 8-bit memory which removed in simulation top
As per requirement Data error corresponds to 8-bit ECC/Data memory which will not present on hardware is acceptable.
But will hardware behavior same as simulation(64-bit memory working properly) or there is some operations not considered in simulation may impact in actual hardware due to absence of 8-bit memory.