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Participant msk_fpga
Participant
471 Views
Registered: ‎02-12-2018

[DDR4] MIG PHY RIU_OR

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Hi,

 

I would like to know that how RIU_VALID signal of RIU_OR in MIG PHY is working to go "LOW" or "HIGH".

I read the HSSIO, SelecIO (UG571), and PG150 but, it just mentioned connections and configurations between BITSLICE_CONTROL and RIU_OR module.

RIU_OR is primitive. BUT, i think, RIU_OR signals are connected to some operation.

What signals make the RIU_VALID signal in RIU_OR? and Why RIU_VALID signal is set to LOW?

 

Thank you a lot for you in advance.

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Participant msk_fpga
Participant
386 Views
Registered: ‎02-12-2018

回复: [DDR4] MIG PHY RIU_OR

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Yes, you right.

Simulation file shows that the RIU_VALID not used is 11bits. Real operating shows that the RIU_VALID is 20bits.

 

i resolve the problem. modify the register sets as remove the WL_DLY_RNK makes the operating working well. Because WL_DLY_RNK conficts with RL_DLY_RNK and then, RL_DLY_RNK is waiting for the write to registers.

 

If someone meet this problem, i suggest that you set the registers to test conditions.

 

Thank you for your kind reply, kren!

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Xilinx Employee
Xilinx Employee
453 Views
Registered: ‎08-21-2007

回复: [DDR4] MIG PHY RIU_OR

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I suggest you can run simualtion on DDR4 IP example design and learn the timing of RIU_OR.

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Participant msk_fpga
Participant
445 Views
Registered: ‎02-12-2018

回复: [DDR4] MIG PHY RIU_OR

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I ran the simulation.

 

but, RIU_VALID in simulation stay on high-z. and Simulation source code in example design is behavial code that is differenct mig_ddr4_phy code to doing real board.

How can i change for moving riu2clb_valid signal?

 

capture.PNG

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Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎08-21-2007

回复: [DDR4] MIG PHY RIU_OR

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Are you trying to learn RIU_OR behavior for modifing the MIG PHY?

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Participant msk_fpga
Participant
431 Views
Registered: ‎02-12-2018

回复: [DDR4] MIG PHY RIU_OR

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Yes. i want to learn to modify the MIG PHY.

I want to deal with the RIU. But, when i write the value to RIU in calibration stage, RL_DLY_RNK registers are not written exactly relative to RIU_VALID signal..

So, i find the documents connections from & to RIU_VALID signal. However, as i said before, RIU_OR include RIU_VALID signal module is just primitive so, i don't see inside the module.

Can i deal with or change the signal of RIU_VALID?

If i want to modify the signal value of RIU_VALID, the only method is physical hardware change? Can't change the value using verilog (in software)? (the reason why is that riu_or and bitslice_control is primitive..?)

 

ps) PHY simulation file is just xiphy_behave file... it's absoultely different from the real phy source code i think..

 

Thank you for your advice and kind reply, kren.

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Xilinx Employee
Xilinx Employee
395 Views
Registered: ‎08-21-2007

回复: [DDR4] MIG PHY RIU_OR

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I didn't find the 12-bit vector in my test project. Which port are you looking at? The "RIU_VALID" ouput of BITSLICE_CONTROL or "RIU_RD_VALID" output of RIU_OR?

 

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Participant msk_fpga
Participant
387 Views
Registered: ‎02-12-2018

回复: [DDR4] MIG PHY RIU_OR

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Yes, you right.

Simulation file shows that the RIU_VALID not used is 11bits. Real operating shows that the RIU_VALID is 20bits.

 

i resolve the problem. modify the register sets as remove the WL_DLY_RNK makes the operating working well. Because WL_DLY_RNK conficts with RL_DLY_RNK and then, RL_DLY_RNK is waiting for the write to registers.

 

If someone meet this problem, i suggest that you set the registers to test conditions.

 

Thank you for your kind reply, kren!

View solution in original post

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