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Visitor bschwerdt
Visitor
407 Views
Registered: ‎01-10-2020

DDR4 MIG VHDL simulation in Riviera

I have a DDR4 controller that I generated in Vivado 2019.2, MIG 2.2.  I am attempting to simulate the behavioral VHDL netlist in Aldec Riviera-Pro.  The controller is sitting idle, and seemingly not finishing the initialization sequence.  Namely, port c0_ddr4_reset_n (active low) remains low, and port c0_init_calib_complete (active high) remains low.

Before the controller goes idle, there is some activity on the adr, ba, bg, cke, odt, ck_t, and ck_c pins.  Then all but the ck_t/ck_c clocks stop.  This is shown in the screen capture attached.  The capture goes to 2us, but no further activity occurs beyond that point.  I have run the simulation as long as 20ms.

Is the controller attempting to perform a calibration routine?  Isn't this supposed to be turned off for simulation?

 

ddr4_sim.PNG
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11 Replies
Xilinx Employee
Xilinx Employee
342 Views
Registered: ‎08-21-2007

回复: DDR4 MIG VHDL simulation in Riviera

According to pg150, only behavirol simulation is supported. 

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Xilinx Employee
Xilinx Employee
337 Views
Registered: ‎08-21-2007

回复: DDR4 MIG VHDL simulation in Riviera

At the initial, there's the stage of calibration which cannot be turned off.

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Visitor bschwerdt
Visitor
312 Views
Registered: ‎01-10-2020

回复: DDR4 MIG VHDL simulation in Riviera

How long should I expect this calibration to take?  I have run the simulation for 10s of milliseconds, and it never seems to finish calibration.

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Xilinx Employee
Xilinx Employee
293 Views
Registered: ‎08-21-2007

回复: DDR4 MIG VHDL simulation in Riviera

It takes less than 10us. Riviera is not t our supported third party simulator. Can you verilog behavoral simulation successfully in Vivado and other third-part simulator (Modelsim, IES, VCS Questa, etc) ?

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Visitor bschwerdt
Visitor
280 Views
Registered: ‎01-10-2020

回复: DDR4 MIG VHDL simulation in Riviera

I have not tried simulating in Vivado.

The IP generator creates a _sim_netlist.vhd file.  Is this all that is needed for simulation?  I am compiling and running that.  I have successfully compiled unisim for Riviera, so I don't understand why this does not work.

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Visitor bschwerdt
Visitor
258 Views
Registered: ‎01-10-2020

回复: DDR4 MIG VHDL simulation in Riviera

If the memory controller's outputs are open / undriven, does the calibration routine still complete in 10us?  Or do I need something to simulate the interactions from the DDR4 chip itself?

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Mentor watari
Mentor
252 Views
Registered: ‎06-16-2013

回复: DDR4 MIG VHDL simulation in Riviera

Hi @bschwerdt 

 

I guess MIG requires result of calibration stage (write leveling, read leveling and adjustment of eye-pattern) if using netlist.

However, it is hard to emulate them by testbench with netlist.

So, I guess Xilinx only support behaiviour simulation without calibration stage.

 

Best regards,

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Visitor bschwerdt
Visitor
249 Views
Registered: ‎01-10-2020

回复: DDR4 MIG VHDL simulation in Riviera

Interesting.  Can I generate the behavioral model without the calibration stage?  It is not immediately apparent to me how I would do that.  I don't see an option in the MIG IP generator.

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Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎08-21-2007

回复: DDR4 MIG VHDL simulation in Riviera

No, calibration stage canno the skipped in behavirol simulation.

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Visitor bschwerdt
Visitor
182 Views
Registered: ‎01-10-2020

回复: DDR4 MIG VHDL simulation in Riviera

If the memory controller's outputs are open / undriven, does the calibration routine still complete in 10us?  Or do I need something to simulate the interactions from the DDR4 chip itself?

 

I never got an answer to this.

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Xilinx Employee
Xilinx Employee
144 Views
Registered: ‎08-21-2007

回复: DDR4 MIG VHDL simulation in Riviera

No, there should be stable clock on the sys_clk intput and sys_rst should be released after sys_clk get stable.

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