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785 Views
Registered: ‎01-28-2018

DDR4 MiG Clocking / VCU108

Hi,

I have a design on the VCU108 with 2 DDR4 MiGs, design tool is VIVADO 2018.3.

I designed according to PG150, page 87.

On the image attached I have added some information about the signal names I used.

Here is the VHDL code:

IBUFDS_Inst0 : IBUFDS
  port map (
    I => c0_sys_clk_p,
    IB => c0_sys_clk_n,
    O => DDR4_If_Clk_3
    );

BUFG_Inst2 : BUFG
  port map (
    I => DDR4_If_Clk_3,
    O => DDR4_If_Clk_0
    );

clk_wiz_0_Inst : clk_wiz_0
  port map (
   clk_out1 => DDR4_If_Clk_1,
   clk_out2 => Clk_0,       // 150 MHz for PL
   reset => RES,
   clk_in1 => DDR4_If_Clk_0
  );

BUFG_Inst0 : BUFG
  port map (
    I => DDR4_If_Clk_1,
    O => DDR4_If_Clk_2
    );

BUFG_Inst1 : BUFG
  port map (
    I => Clk_0,
    O => CLK       // 150 MHz for PL
    );

ddr4_0_Inst : ddr4_0
  PORT map (
    c0_init_calib_complete => c0_init_calib_complete_0,
     c0_sys_clk_i => DDR4_If_Clk_2, ......

ddr4_1_Inst : ddr4_1
  PORT map (
    c0_init_calib_complete => c0_init_calib_complete_1,
     c0_sys_clk_i => DDR4_If_Clk_2, .....

In my opinion, all is designed exactly according to PG150.

Can anybody explain me why I get this error message from implementation:

[Mig 66-99] Memory Core Error - [ddr4_1_Inst] Either port(s) c0_sys_clk_p, c0_sys_clk_n is/are not placed or un-supported clocking structure/circuit for memory ip instance. Please refer to clocking section of PG150 for supported clocking structures.

[Opt 31-306] MIG Core Generation Failed.

Any suggestions for fixing this issue are highly appreciated.

Norbert

 

 

Clocking_DDR4.jpg
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7 Replies
Scholar jg_bds
Scholar
734 Views
Registered: ‎02-01-2013

Re: DDR4 MiG Clocking / VCU108

 

You did not include the pin numbers for your clock pins. Are the differential clock signals entering the FPGA on the correct, GC-capable pins?

2019-02-18_11-17-38.jpg

-Joe G.

 

Scholar jg_bds
Scholar
724 Views
Registered: ‎02-01-2013

Re: DDR4 MiG Clocking / VCU108

 

Got a chance to look at this more closely...

I'm not sure what you're doing with all of that VHDL, but you're not supposed to be re-creating the Clocking Structure Diagram from the PG that you included in your post. Your job is to connect the system clock input to the MIG-created module(s). Each underlying module will contain its own MMCM and the necessary clocking structures beyond the MMCM.

Since you'll be sharing a clock source between two MIGs (because that's the way it's done on the VCU108), you'll probably want to check-out the section titled Sharing of Input Clock Source (sys_clk_p) on page 88 of the PG. You're likely missing a critical "set_property CLOCK_DEDICATED_ROUTE BACKBONE..." constraint.

-Joe G.

 

 

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708 Views
Registered: ‎01-28-2018

Re: DDR4 MiG Clocking / VCU108

Hi,

thanks for your reply.

In my .xdc file I included:

set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p]
set_property PACKAGE_PIN G31 [get_ports c0_sys_clk_p]
set_property PACKAGE_PIN F31 [get_ports c0_sys_clk_n]
set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n]

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]

So this should be ok.

I cannot see from the PG150 document which bufs and MMCMs I have to implement and which ones will be created by the IP generator.

I would appreciate if you could tell me what to change in my design in order to get it work.

Regards

Norbert

 

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Scholar jg_bds
Scholar
700 Views
Registered: ‎02-01-2013

Re: DDR4 MiG Clocking / VCU108

 

This builds for me (through Generate Bitstream):

2019-02-19_7-08-54.jpg

using these constraints:

2019-02-19_7-12-00.jpg

The first utility buffer is a board-specific IBUFDS:

2019-02-19_7-52-21.jpg

The second buffer is a simple BUFG.

-Joe G.

 

690 Views
Registered: ‎01-28-2018

DR4 MiG Clocking / VCU108

Hi again,

thank you for your reply.

You used a block design. I avoided this until now since you cannot uncheck the AXI Interface for the DDR4 blocks. I do not need AXI since my memory will be connected only to fabric logic.

According to your proposal I changed my design as follows:

IBUFDS_Inst0 : IBUFDS
  port map (
    I => c0_sys_clk_p,
    IB => c0_sys_clk_n,
    O => DDR4_IfClk0
    );

BUFG_Inst0 : BUFG
  port map (
    I => DDR4_IfClk0,
    O => DDR4_IfClk1
    );

ddr4_0_Inst : ddr4_0
  PORT map (
     ......
     c0_sys_clk_i => DDR4_IfClk1,
     ......
    addn_ui_clkout1 => CLK,                      // 150 MHz Clock for PL
    addn_ui_clkout2 => DDR4_ClkOut0   //  300 MHz Clock for PL
    );

ddr4_1_Inst : ddr4_1
  PORT map (

    ........
    c0_sys_clk_i => DDR4_IfClk1,
   .....
    );

I used the .xdc constraints as you proposed.

The design compiles and implements, but now I get a lot of timing errors, partially from within the MIG cores.

So I would like to test your block design. Can you please send me information about the configuration of the AXI interconnect block and the DDR4 memory blocks?

In particular, which clocking options did you chose? Custom Clock / buffer / no buffer?

I entered the design as shown on your image but I get this error message:

CRITICAL WARNING: [BD 41-1356] Address block </ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK> is not mapped into </jtag_axi_0/Data>. Please use Address Editor to either map or exclude it.

I think I did not match your block configuration for AXI interconnect interface or jtag AXI interface.

Regards

Norbert

 

AXI_Uncheck.jpg
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Scholar jg_bds
Scholar
684 Views
Registered: ‎02-01-2013

Re: DR4 MiG Clocking / VCU108

 

Timing will be tight. Good design practice would be needed to expand what I've got working into a larger, more useful system.

Most IP provided by Xilinx for use in IP Integrator is configured with AXI interfaces, because that's the primary way of hooking-up IP blocks in IPI. When dealing with a unknown logic, it's best to either: 1) create an Example Design for an IP plucked from the IP library outside of IPI, or 2) whip-up a system in IPI using what they give you. I often prefer the latter--at least to get started.

Once either path has been taken through Synthesis, it's possible to inspect the Synthesized design (viewing a block diagram or reading individual HDL files) to better understand the requirements for properly fashioning the design. If you push (4 or 5 layers?) into the HDL, you can actually see the code that handles the clock parameters, such as the one controlling the buffering of sys_clk.

Attached is a ZIP with my BD-based design. I haven't had a chance to test this extraction. The header of the .TCL file shows the original, relative locations of the included source files. You can either position them in a similar location (to where you invoke the .TCL file) or just modify the TCL file so it can find them where you position them.

-Joe G.

649 Views
Registered: ‎01-28-2018

Re: DR4 MiG Clocking / VCU108

Hi again,

sorry, but I still have the problem and cannot find a solution.

In order to give you an idea of my concept, I attach a block schematic of the design.

The design contains 2 DDR4 MIGs, but no processor. There are a lot of PL blocks which may send a data read request to the DDR4 at any time.

These requests are sent to an arbitration controller which in turn generates the control signals for the DDR4 memories and organizes the data flow.

The arbitration controller and the DDR4 Data Buffers are supplied with a 300 MHz clock since the DDR4 may deliver output data at this rate. The PL logic is connected to a 150 MHz clock.

What makes me wonder is that the design worked in late 2018 under VIVADO 2018.2. I could implement it without error messages and it worked on the real VCU108 board.

The problems came up when I upgraded to 2018.3. I could not fix these problems and went back to 2018.2 2 weeks ago.

When I re-opened the design the tool complained about deprecated IP blocks and updated them. Now the design can no longer be implemented, even not with VIVADO 2018.2.

I have tried many combinations of clock strategies and DDR4 configurations, none of them work. On the image attached you see the configuration where the differential clock is first fed into a IBUFDS and then into a BUFG. The upper DDR4 is configured with 2 output clocks, 300 MHz and150 MHz, the latter is used for the PL locgic.

I also have tried to configure the upper DDR4 for differential clock supply, according to PG 150. None of these concepts work. Either the tool complains aboute invalid clock structures or I get a lot of timing violation messages upon implementation.

 I would appreciate very much if someone could give me some help how to fix these problems.

Norbert

 

DDR4Arbiter.JPG
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