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mubahceci
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Registered: ‎11-05-2018

DDR4 Mig IP and Traffic Generation in Simulation

Hi,

I have tried to use MIG IP in my project to get access of the DDR4, but I have some questions for this process.

First of all, I am using KCU105 board, and I created a mig ip with standard settings. After my core was generated, I opened exampled design with right click. Then, it made an example_top file. In this file, I added my submodules like state machine that control my write and read process between fifo and mig ip inputs.It shows my submodules in example_topIt shows my submodules in example_top

Secondly,  I also added my custom inputs to example_top to send data and see them on simulation. When I looked the write path of mig ip, I think my state machine works probably. In simulation, I increase the data with each input_fifo clock. Each 512 bit includes 16 32bit data, so in hexadecimals, it looks like 0000000..... | 00000010..... | 00000020..... | 00000030...... 

100 ps delay at app_rdy and it shows that current address takes the right data.100 ps delay at app_rdy and it shows that current address takes the right data.

 

Same delay happens.Same delay happens.

Thirdly, when my state machine goes to read operation. It always shows 0. I guess that I am missing some points in traffic generation. Can anyone how I can create custom simulation to see my value given address value.

For read path, ddr rd_data channel shows 0s.For read path, ddr rd_data channel shows 0s.

Thanks,

Umut

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kren
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Registered: ‎08-21-2007

Please check whether the write/read operation at the DDR4 interface are correct. You can look into the signals ddr4_adr, ddr4_dq/ddr4_dqs.

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mubahceci
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Registered: ‎11-05-2018

Hi,
I think my write path operation is correct if we look at second and third screenshots. Each address gets own data when app_en, app_rdy, app_wdf_wren, app_wdf_rdy are high. However, I don't know how I show read data with example design that is edited by me. Do you have any advice to see read data from read channel? Thanks.
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kren
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Registered: ‎08-21-2007

I found there's confliction on the app_rd_data. please check your deisgn to fix this firstly. 

I can see the app_rd_data_valid was asserted. Were the data correct when app_rd_data_valid='1'?

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behnam_2705new
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Registered: ‎03-16-2019

as I can see you have a problem in the writing process.

you should consider that data stream is separated from the command stream, for example, you should set command(write or read) than change address then wait to catch app_rdy signal if this signal is not asserted you should re-send the command. 

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