09-26-2019 12:05 AM - edited 09-26-2019 12:12 AM
I have tried to use MIG IP in my project to get access of the DDR4, but I have some questions for this process.
First of all, I am using KCU105 board, and I created a mig ip with standard settings. After my core was generated, I opened exampled design with right click. Then, it made an example_top file. In this file, I added my submodules like state machine that control my write and read process between fifo and mig ip inputs.
Secondly, I also added my custom inputs to example_top to send data and see them on simulation. When I looked the write path of mig ip, I think my state machine works probably. In simulation, I increase the data with each input_fifo clock. Each 512 bit includes 16 32bit data, so in hexadecimals, it looks like 0000000..... | 00000010..... | 00000020..... | 00000030......
Thirdly, when my state machine goes to read operation. It always shows 0. I guess that I am missing some points in traffic generation. Can anyone how I can create custom simulation to see my value given address value.
09-27-2019 02:43 AM
Please check whether the write/read operation at the DDR4 interface are correct. You can look into the signals ddr4_adr, ddr4_dq/ddr4_dqs.
09-27-2019 05:20 AM
10-11-2019 01:40 AM
I found there's confliction on the app_rd_data. please check your deisgn to fix this firstly.
I can see the app_rd_data_valid was asserted. Were the data correct when app_rd_data_valid='1'?
10-15-2019 04:01 AM
as I can see you have a problem in the writing process.
you should consider that data stream is separated from the command stream, for example, you should set command(write or read) than change address then wait to catch app_rdy signal if this signal is not asserted you should re-send the command.