DDR4 RDIMM: DQ and DQS lines alignment on PCB

[DDR4]

Dear Community,

I couldn't find a clear answer in the documentation on the question: shall the data within a byte be aligned for

DDR4 RDIMM design, if 2 DQS signals are presented for a single byte? (x4)

Let's assume, I'm using x4 memory module controller, like M393A8K40B21-CTC.

Will it work, if tetrads are not aligned within a byte?

Please, advise.

Thanks

[kren · Accepted solution]

The skew requirement it for DQ(Data) to associated DQS. In your case, it should the 4 bit data to the associated DQS.

[DDR4]

Thank you @kren,

It became clear now.

BR