cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Visitor
Visitor
377 Views
Registered: ‎10-15-2020

DDR4 RDIMM: DQ and DQS lines alignment on PCB

Jump to solution

Dear Community,

 

I couldn't find a clear answer in the documentation on the question: shall the data within a byte be aligned for

DDR4 RDIMM design, if 2 DQS signals are presented for a single byte? (x4)

Let's assume, I'm using x4 memory module controller, like M393A8K40B21-CTC.

Will it work, if tetrads are not aligned within a byte?

Please, advise.

Thanks

1 Solution

Accepted Solutions
Moderator
Moderator
256 Views
Registered: ‎08-21-2007

The skew requirement it for DQ(Data) to associated DQS. In your case, it should the 4 bit data to the associated DQS.

-----------------------------------------------------Please don't forget to give kudos or accept as solution if information provided is helpful.---------------------------------------------------------------------

View solution in original post

2 Replies
Moderator
Moderator
257 Views
Registered: ‎08-21-2007

The skew requirement it for DQ(Data) to associated DQS. In your case, it should the 4 bit data to the associated DQS.

-----------------------------------------------------Please don't forget to give kudos or accept as solution if information provided is helpful.---------------------------------------------------------------------

View solution in original post

Visitor
Visitor
241 Views
Registered: ‎10-15-2020

Thank you @kren

0 Kudos
Reply