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DDR4
Visitor
Visitor
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Registered: ‎10-15-2020

DDR4 RDIMM: DQ and DQS lines alignment on PCB

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Dear Community,

 

I couldn't find a clear answer in the documentation on the question: shall the data within a byte be aligned for

DDR4 RDIMM design, if 2 DQS signals are presented for a single byte? (x4)

Let's assume, I'm using x4 memory module controller, like M393A8K40B21-CTC.

Will it work, if tetrads are not aligned within a byte?

Please, advise.

Thanks

1 Solution

Accepted Solutions
kren
Moderator
Moderator
387 Views
Registered: ‎08-21-2007

The skew requirement it for DQ(Data) to associated DQS. In your case, it should the 4 bit data to the associated DQS.

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kren
Moderator
Moderator
388 Views
Registered: ‎08-21-2007

The skew requirement it for DQ(Data) to associated DQS. In your case, it should the 4 bit data to the associated DQS.

-----------------------------------------------------Please don't forget to give kudos or accept as solution if information provided is helpful.---------------------------------------------------------------------

View solution in original post

DDR4
Visitor
Visitor
372 Views
Registered: ‎10-15-2020

Thank you @kren

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