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Observer
Observer
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Registered: ‎04-23-2019

DDR4 command/address/clk routing between VDD and Ground planes

Hello,

If the impedance is correct, is there a problem with routing DDR CAC signals between power and ground planes ?

Thanks,

Emmett

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Moderator
Moderator
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Registered: ‎08-21-2007

Yes, you can refer to the "reference stackup" section in ug583: https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

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Observer
Observer
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Registered: ‎04-23-2019

Hi kren,

I saw that before, but the innermost signal layer is between GND and PWR/GND.

That could mean the power might be VDD of the DRAM or that it must be GND.

Don't want top assume anything.

Thanks,

Emmett

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Moderator
Moderator
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Registered: ‎11-09-2017

Hi @ebradford 

Its depends on routing topology, for example fly-by routing or clamshell topology.

Detailed information is documented in ug583, link provided below

https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

Regards
Pratap

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