02-04-2020 10:35 AM
If the impedance is correct, is there a problem with routing DDR CAC signals between power and ground planes ?
02-05-2020 01:22 AM
Yes, you can refer to the "reference stackup" section in ug583: https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf
02-05-2020 06:36 AM
I saw that before, but the innermost signal layer is between GND and PWR/GND.
That could mean the power might be VDD of the DRAM or that it must be GND.
Don't want top assume anything.
02-05-2020 07:34 AM
Its depends on routing topology, for example fly-by routing or clamshell topology.
Detailed information is documented in ug583, link provided below