cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
hsajja
Visitor
Visitor
4,221 Views
Registered: ‎10-05-2017

DDR4 model memory backdoor loading

I want to backdoor load DDR4 micron memory model in simulation, how can I do that?

0 Kudos
6 Replies
ryana
Moderator
Moderator
4,145 Views
Registered: ‎11-28-2016

Hello @hsajja,

 

In the Micron DDR4 Verilog models there's a file called memory_file.txt. Inside of it are the instructions on how to pre-load the memory with data. Looks pretty straight forward. Next I looked at their supplied test benches.

They enable the model called 'golden_model'
ddr4_model #(.CONFIGURED_DQ_BITS(CONFIGURED_DQ_BITS), .CONFIGURED_DENSITY(CONFIGURED_DENSITY), .CONFIGURED_RANKS(CONFIGURED_RANKS))
golden_model(.model_enable(model_enable), .iDDR4(iDDR4));

In the subtest part of the test bench they load memory_file.txt
golden_model.initialize_memory_with_file("memory_file.txt")

From there you can modify our TB to add the line to "initialize_memory_with_file" with our model in the sim_tb_top.sv.

mushihao
Observer
Observer
3,322 Views
Registered: ‎05-07-2019

Hi @ryana ,

I am using Vivado 2018.3 and after I generated the example tb, I didn't see memory_file.txt and I couldn't find the instructions on how to backdoor loading the ddr model.

Can you please elaborate or provide a new pointer on the file format and how to use it?

 

Thanks,

Hao

0 Kudos
deepalir
Xilinx Employee
Xilinx Employee
3,007 Views
Registered: ‎02-21-2019

Hi @mushihao 

It doesn’t look like the “memory_file.txt” is included anymore like it was in earlier versions so you would have to download the simulation files, as an example, here you can download the files under “Simulation Models”

https://www.micron.com/products/dram/ddr4-sdram/part-catalog/mt40a1g16knr-062e


Please mark the Answer as "Accept as solution" if the information provided is helpful.
Also, don't forget to give Kudos to a post which you think is helpful.


 

summerweix
Visitor
Visitor
2,588 Views
Registered: ‎10-05-2019

Hi @deepalir ,

I'm trying to do backdoor load for ddr4 on vcu118 board, in the sim_tb_top.sv ddr4_model is instantiated like this:

if (DQ_WIDTH/16) begin: mem

DDR4_if #(.CONFIGURED_DQ_BITS (16)) iDDR4[0:(RANK_WIDTH*NUM_PHYSICAL_PARTS)-1]();

for (r = 0; r < RANK_WIDTH; r++) begin:memModels_Ri2
for (i = 0; i < NUM_PHYSICAL_PARTS; i++) begin:memModel2
ddr4_model #
(
.CONFIGURED_DQ_BITS (16),
.CONFIGURED_DENSITY (CONFIGURED_DENSITY)
) ddr4_model(
.model_enable (model_enable),
.iDDR4 (iDDR4[(r*NUM_PHYSICAL_PARTS)+i])
);
end
end


When I added ddr4_model.initialize_memory_with_file("memory_file.txt") the compile will report error saying cannot fine ddr4_model, do you have any suggestion?

0 Kudos
deepalir
Xilinx Employee
Xilinx Employee
2,532 Views
Registered: ‎02-21-2019

@summerweix 

As mentioned earlier, the “memory_file.txt” is not included anymore, so you would have to download the simulation files from Micron. Inside of memory_file.txt are instructions on how to pre-load the memory with data. 

They enable the model called 'golden_model'
ddr4_model #(.CONFIGURED_DQ_BITS(CONFIGURED_DQ_BITS), .CONFIGURED_DENSITY(CONFIGURED_DENSITY), .CONFIGURED_RANKS(CONFIGURED_RANKS))
golden_model(.model_enable(model_enable), .iDDR4(iDDR4));

In the subtest part of the test bench they load memory_file.txt
golden_model.initialize_memory_with_file("memory_file.txt")

From there you can modify our TB to add the line to "initialize_memory_with_file" with our model in the sim_tb_top.sv.


Please mark the Answer as "Accept as solution" if the information provided is helpful.
Also, don't forget to give Kudos to a post which you think is helpful.


 

0 Kudos
zxm02370303
Participant
Participant
1,360 Views
Registered: ‎03-26-2013

HELLO HOW TO IMPLEMENTATE IN TO vivado 2018.3 with

ddr4 sim_tb_top.sv seemes quite different .Thank you.

0 Kudos