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Participant
Participant
2,909 Views
Registered: ‎09-11-2010

DDR4 simulation issue with c0_ddr4_app_wdf_rdy = X

I just upgraded from Vivado 2016.2 to 2017.2 and upgraded all IPs to the latest versions including DDR4 (2.2 Rev 1).  Running my project in simulation everything starts out working as expected, but after running for a while the reads start to take longer than 50 clock cycles and c0_ddr4_app_wdf_rdy goes from 1 to X.  

 

I am running on windows 10 and Avnet Kintex-Ultrascale Development Board (xcku040-fbva676-1-c).

 

Any help would be appreciated.

 

Thanks

 

 

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Participant
Participant
2,830 Views
Registered: ‎09-11-2010

I put in the wrong signal in my original post, it is c0_ddr4_app_rdy that changes to x after a number of operations.   It starts out as x, transitions to 0 until the calibration is complete and then goes to 1.  After a number of read operations it changes from 1 to x causing the project to hang.

 

Any help would be appreciated.

 

Thanks

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Xilinx Employee
Xilinx Employee
2,816 Views
Registered: ‎03-07-2012

What is your simulator and what is the version of your simulator?

Have you tried example design?

 

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Participant
Participant
2,614 Views
Registered: ‎09-11-2010

I am running Vivado Simulator 2017.2.  It worked fine with the DD4 IP and Vivado simulator at 2016.2.

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Xilinx Employee
Xilinx Employee
2,565 Views
Registered: ‎03-07-2012

Does example design have the same issue?

Are there any ports left unconnected?

 

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