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209 Views
Registered: ‎02-23-2019

DDR4 v2.2 ECC signals are missing from the User Interface when ECC is enabled with AXI

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Using Vivado 2019.1, I have the MIG configured as shown below with ECC enabled.  The ECC ports are disable, and I can find no way to enable them.  AR#67455 seems related and offers a tactical patch; however, it explicitly states it applies only to DDR4 v2.0... I'm using v2.2.

Is there a way to enable ECC ports on v2.2?  Is this patch applicable?  Any help would be appreciated... thanks!

ChrisP

MIG_config.PNG

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Registered: ‎11-28-2016

Re: DDR4 v2.2 ECC signals are missing from the User Interface when ECC is enabled with AXI

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Hello cpawlowski@planetiq.com ,

Based on what I'm seeing in the screenshot it looks like you have the AXI4 option enabled in the configuration GUI.  This is the expected behavior because when the AXI4 option is enabled then you will monitor the ECC status through the C0_DDR4_S_AXI_CTRL AXI-Lite interface.  You can see the details about this in PG150 in the AXI4-Lite Slave Control/Status Register Interface Block section starting on page 148.  A link is in my signature.  When you have the AXI4 interface option disabled then these native app_interface type signals are brought out to the top level of the IP.  We don't expose these native app_interface ECC status signals when the AXI option is enabled because logically there's no point in having non-AXI signals in an AXI based design.

AXI Enabled:
axi_enabled.PNG

AXI Disabled:
axi_disabled.PNG

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Moderator
Moderator
199 Views
Registered: ‎11-28-2016

Re: DDR4 v2.2 ECC signals are missing from the User Interface when ECC is enabled with AXI

Jump to solution

Hello cpawlowski@planetiq.com ,

Based on what I'm seeing in the screenshot it looks like you have the AXI4 option enabled in the configuration GUI.  This is the expected behavior because when the AXI4 option is enabled then you will monitor the ECC status through the C0_DDR4_S_AXI_CTRL AXI-Lite interface.  You can see the details about this in PG150 in the AXI4-Lite Slave Control/Status Register Interface Block section starting on page 148.  A link is in my signature.  When you have the AXI4 interface option disabled then these native app_interface type signals are brought out to the top level of the IP.  We don't expose these native app_interface ECC status signals when the AXI option is enabled because logically there's no point in having non-AXI signals in an AXI based design.

AXI Enabled:
axi_enabled.PNG

AXI Disabled:
axi_disabled.PNG