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Visitor linyuan_66
Visitor
580 Views
Registered: ‎11-04-2019

DDR4 vivado2018

sir! I encounter a problem.

  I generate a ddr4 controller , but there are two error in my project.

[Route 35-19] Driver is not a routable pin (driver inst term u_top/ddr_axi_controller/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[2].u_ddr_iob_byte/genBuf[6].genBuf.OBUFDS/O, cell type OBUF, site type HPIOB_M). design will not pass DRC check. Router will skip the net .

  This the message given by VIVADO201801 .  I can't generate bitstream.

  Please help me , thank you very much!

 

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16 Replies
Xilinx Employee
Xilinx Employee
546 Views
Registered: ‎01-09-2019

Re: DDR4 vivado2018

Hello @linyuan_66 

Have you generated the DDR4 example design (right-click on the DDR IP and click "Create IP Example Design...")?

That will show a working design and how the controller should be routed.

Have you changed anything in the layout/clocking/pinout of the DDR controller?  Can you provide more information on your design and what exactly you have done to generate this issue?

Thanks,
Caleb
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Visitor linyuan_66
Visitor
525 Views
Registered: ‎11-04-2019

Re: DDR4 vivado2018

sir!

  I haven't change any thing about the ddr4_controller.

  The picture is the config about the controller, System Clock Option is Differential,

the c0_sys_clk_p is 250M CLK from xcvu9p (GCIO).

cfg.png
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Xilinx Employee
Xilinx Employee
506 Views
Registered: ‎01-09-2019

Re: DDR4 vivado2018

@linyuan_66 

In the future can you use the "Snipping Tool" on Windows, or on Linux there are plenty of screenshot tools that can be used for free.  This will help with our ability to read the images sent.

Otherwise, the error you show looks to be in Synthesis or Implementation, where exactly are you seeing that error show up?

In Synthesis you will need to determine the pin planning for the eventual pinout of the DDR.  This means you will need to have additional steps in Synthesis before you will be able to get the design to complete Implementation.

Is this design the example design?  If not, please try with the example design using the configuration of your DDR controller.

Have you tried with the default clocking and not choosing your own MMCM ratios?  Does that allow you to get passed this issue?

Thanks,
Caleb
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Visitor linyuan_66
Visitor
479 Views
Registered: ‎11-04-2019

Re: DDR4 vivado2018

sir,

  I close the my MMCM ratios, but it apperas the same error.
The error not the pin out,  it is in the blackbox, the rtl uses the generation to produce some genBuf[*], but only the genBuf[6] have error, others are right.

 

Please help me , thank you very much.

 

 

 

ddr4_controller.png
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Xilinx Employee
Xilinx Employee
461 Views
Registered: ‎01-09-2019

Re: DDR4 vivado2018

@linyuan_66 

Please try running the DDR example design.  This should pass routing, but I want to make sure before going any further.  Otherwise, this isn't a particular issue with the DDR controller as the controller has been able to route properly in many designs.  Here is an AR which talks about how to debug routing issues: https://www.xilinx.com/support/answers/53854.html

I would also be interested in how you are constraining the design.  Can you try setting the DONT_TOUCH property like in this forum post? https://forums.xilinx.com/t5/Implementation/Implementation-Complete-but-many-unroute-nets/td-p/825198

Thanks,
Caleb
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Visitor linyuan_66
Visitor
399 Views
Registered: ‎11-04-2019

Re: DDR4 vivado2018

sir:

   DONT_TOUCH can't solve the problem.  The error is the follow:

   Name    Cell Pins     Flat Pins    Driver        Route States

   CK_C[0]    1          2        _           Routable but not routed

   CK_T[0]    1          2        _           Routable but not routed

  I just only creat a clock on the CK_C pin, haven't constained ohters.

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Visitor linyuan_66
Visitor
394 Views
Registered: ‎11-04-2019

Re: DDR4 vivado2018

 
CK.PNG
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Xilinx Employee
Xilinx Employee
359 Views
Registered: ‎01-09-2019

Re: DDR4 vivado2018

@linyuan_66 

Is your input differential clock to the DDR IP coming from off the FPGA?  Can you show the block diagram of your design?

Thanks,
Caleb
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Visitor linyuan_66
Visitor
326 Views
Registered: ‎11-04-2019

Re: DDR4 vivado2018

The CLK_n come from xcvu9p D12, CLK_p come from xcvu9p E12.

I just find the differential clock from SLR2 with DDR4_C1.

The CLK_n/p just only connect to the DDR4_controller without through any pad and buf.
Does CK_T need constrain ? The error show the CK_T/CK_C can routable but not route, is it need special constain?

The picture is the block diagram of my design.

ddr4_sys.PNG
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Xilinx Employee
Xilinx Employee
310 Views
Registered: ‎01-09-2019

Re: DDR4 vivado2018

@linyuan_66 

Having the differential clock connected from off-chip is correct.  What do your constraints look like?  I don't believe you should need a special constraint.  The error looks to be like you have multiple BUFGs connected in series for the CK_T/C.

The DDR controller should do the constraining properly for the interface clock if given a proper clock and the correct placement of all the DDR pins.  Can you double check with the PG150 pin guides (this starts on page 104)?

Thanks,
Caleb
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Visitor linyuan_66
Visitor
282 Views
Registered: ‎11-04-2019

Re: DDR4 vivado2018

Sir,
I have a problem again.
The controller use axi interface, but the work frequency is (750-1600ps)*4. Can i let axi work at 100 Mhz ?
I use a 512K bram, but the timing fail, do you have some good advice?
Thank you very much!
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Visitor linyuan_66
Visitor
262 Views
Registered: ‎11-04-2019

Re: DDR4 vivado2018

sir, Does VIVADO contain a cell which produce a power on reset?
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Xilinx Employee
Xilinx Employee
244 Views
Registered: ‎01-09-2019

Re: DDR4 vivado2018

@linyuan_66 

We have a maximum frequency that you can run the AXI interface, but you can also run slower.  100 MHz is an acceptable rate to run the AXI interface at if desired.

In terms of a cell for reset, have you looked at the IP titled Processor System Reset?  That takes in a clock input and provides a reset output that is synchronous to that clock domain.

Thanks,
Caleb
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Visitor linyuan_66
Visitor
225 Views
Registered: ‎11-04-2019

Re: DDR4 vivado2018

   If I want axi working at 100Mhz,  how to config the controller ? (vivado201802.ddr4)

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217 Views
Registered: ‎11-21-2019

Re: DDR4 vivado2018

The i.MX 6DualPlus/6QuadPlus Multi Mode DDR Controller (MMDC) can be used to program the
DDR3/DDR3L device for proper operation. This is achieved by an initialization sequence of specific
register writes prior to accessing the external DDR device. Programming of the DDR3/DDR3L memory
device is dependent on various factors such as:
• DDR memory timing and speed grade
• Memory layout (Fly-by, T topology) https://redtube.vin
• Bus width (x32, x64)
• Drive Strength and Board layout
Since the above factors are dependent on the customer’s DDR memory selection, use case and board
design, common programming recommendations cannot be provided as they will be unique for each
customer design. NXP provides a DDR3 MMDC register programming aid to help in configuring these
specific parameters. Contact your NXP field engineer or sales representative for the i.MX
6DualPlus/6QuadPlus DDR3 Register Programming Aid.

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Xilinx Employee
Xilinx Employee
187 Views
Registered: ‎01-09-2019

Re: DDR4 vivado2018

@smithclarkson1 

I think you responded to the wrong thread as this is related to a DDR4 controller and device.

@linyuan_66 

If you are trying to run the DDR controller at a slower speed that would mean a slower clock speed and you can find how to change that in PG150 page 88.  I will say that will be absolutely detrimental to your performance, and you probably will be better off using an AXI Smartconnect to perform clock conversion to a higher frequency that the DDR Controller desires.

In terms of timing failures, that is likely something in your design that would cause that as the DDR Controller would not fail timing.  I am not sure what your design is doing so I cannot say what would get you to pass timing.  I would suggest confirming that all required pin rules are met based on PG150 page 104.

Thanks,
Caleb
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