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goghvan005
Observer
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Registered: ‎06-19-2018

DDR4 write leveling error

Hi,

When I initiate my board using ‘psu_init.tcl’, it takes very long time and never be done.

Then I use XSCT to debug the core, the info like this.

微信图片_20191107000902.jpg微信图片_20191107000827.jpg

The DDR write leveling byte8 error.

My FPGA chip is ZU11EG, and the DDR4 is MT40A256M16GE-075E, beside in vivado2018.3 the PS_DDR_controller setting is like this

微信图片_20191107001640.jpg

So,what should I do to make ddr4 working correctly.

Thank you!

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calebd
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Registered: ‎01-09-2019

Hello @goghvan005 

Next time, can you try to take screenshots (on Windows use the snipping tool, on Linux there are a multitude of free equivalent utilities).  This is much easier to read for everyone involved.

Can you try initializing the DDR using an FSBL?  In SDK create an FSBL project and program that onto the board, then run your other project on top of that without resetting or reprogramming the bitstream onto the device.

It looks like calibration isn't completing in your design, can you try running at a slower speed (like 800 MHz)?  Can you try setting 2T timing on and running with that to see if that causes any change in calibration?  The command for enabling 2T timing:

set_property -dict [list CONFIG.PSU__DDRC__ENABLE_2T_TIMING {1}] [get_bd_cells zynq_ultra_ps_e_0]

Otherwise a calibration failure can potentially point towards a failure in hardware.  Are you able to and can you go over UG583 Chapter 2 with a fine-toothed comb to make sure all PCB guidelines are kept?

Thanks,
Caleb
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goghvan005
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Registered: ‎06-19-2018

hello @calebd

I am sorry to reply this topic so late. I try your suggestions, running at 800MHz,but this is not working.And setting 2T timing on and running with that is not working. Also i double check the PCB following UG583,the guidlines are kept.

So I use the command to check the DDR debug register 0xFD080030,the value is 0x808000FF.This value represent that the write latency adjustments error.

Also I check the register 0xFD0807DC,the valus is 0x00000001.

So,how can I solve this error?

Thanks,

goghvan005

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watari
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Registered: ‎06-16-2013

Hi @goghvan005 

 

Would you make sure the different length between each DQS and clock pair ?

 

Best regards,

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calebd
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Registered: ‎01-09-2019

Hi @goghvan005 

What you are seeing with a slowed down interface and 2T timing is that you are passing Write Leveling, is that correct?  If you are getting to Write Latency Adjustment, then you are getting further and so slowing down the interface is helping with this issue.  Are you able to dump those register values into a .txt file?  You should be able to do so like this: https://forums.xilinx.com/t5/Embedded-Development-Tools/SDK-Memory-dump-from-console/td-p/685748

Specifically from UG1085 page 467 shows the write latency adjustment values which would be good to dump from this failed step.  Is there a specific byte that is failing, or is there more than one byte that is failing?

Thanks,
Caleb
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goghvan005
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Registered: ‎06-19-2018

hi @calebd,

The write leveling test pass!

I check tDXnRSR3 for all bytes ,the result is all the bytes are falling.

 

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goghvan005
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Registered: ‎06-19-2018

The register value is dumped into this file.

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goghvan005
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Registered: ‎06-19-2018

Hi @calebd, The file is not right?

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calebd
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Registered: ‎01-09-2019

@goghvan005 

That file was the register dump, and I can see the stage of calibration which is failing and with what values.  Not passing calibration, and when slowing down the interface it allows calibration to run further, usually indicates that there is an issue with your configuration or something related to physical hardware.

Looking at your configuration, it seems correct for the memory device you have chosen.  In terms of hardware, you said you double checked all of the guidelines from UG583.  To confirm that includes the skew requirements for Data, CK, and DQS, as well as the relevant impedance values for each of those lines.  Did you make sure there is appropriate ground stitching underneath your devices (page 57 has an example for a fly by topology)?  Are your decoupling capacitors exactly as specified in UG583 for your power rails?

Have you done any signal integrity tests?  Can you provide those results?  What about power integrity?

The next thing to look at would be to get power and clocking measurements.  This guide talks about the measurements needed, and how to perform those measurements: https://www.xilinx.com/support/answers/62181.html  In addition can you take measurements of some address lines on the CAC bus while calibration is happening?  I would say address bit 3, the differential clock, another address bit (say 5), RAS, and CAS would be good signals to probe.

Thanks,
Caleb
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shekhar_sk6
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Registered: ‎12-04-2018

@goghvan005 @calebd 

Please, can you tell, how did write leveling pass with 800MHz or 2T timing ?

Because I am facing exactly the same issue and even with 800MHz or 2T timing, we cannot pass Write Leveling stage

calebd
Moderator
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1,128 Views
Registered: ‎01-09-2019

@shekhar_sk6 

Could you please create a new post about your issue since it might be related, but have some different behaviors that will need to be addressed?  That way we can best track all issues to help all customers as best as possible.

With regards to why 2T timing or 800 MHz might pass while a higher frequency or 1T timing wouldn't.  That is consistent with some failure in signal or power integrity, or a configuration issue with regards to how the IP is setup compared to the DDR device you are using.  When the Write Leveling step fails it shows that the DDR IP could not calibrate which is the basic requirement to communicate with your physical DDR.

The steps to check are:

1. Look at the DDR configuration and the DDR datasheet going through each setting understanding why each needs to be set to the value it should be.

2. Take good scope probe measurements of the power rails and DDR interface signals to ensure that these are being driven correctly per the datasheet for your device and UG583.

3. Check through each of UG583 and UG1085 guidance on pinouts and layout requirements.

Some useful links:

https://www.xilinx.com/support/answers/62181.html (for best scope probe practices)

https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf (for layout guidance)

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf (understanding the basics of the DDR controller and its pin requirements)

@goghvan005 

This advise may also be useful for your original issue so pointing you to these documents and different steps to take.

Thanks,
Caleb
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patmcn
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Registered: ‎06-27-2019

Thank you very much for this info. I would recommend to add this to the mpsoc boot and configuration resource list.

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