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xlxuserc
Observer
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Registered: ‎08-25-2020

[DRC NSTD-1] and [DRC UCIO-1] - xtp244-zc706-mig-c-2015-4 example cannot generate bitstream

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Dear Sir/Madam, 

when following xtp244-zc706-mig-c-2015-4.pdf MIG example on vivado2017.4, setting on zc706 with the onboard SODIMMs. it keep failing to generate bitstream with 2 errors below when run implementation before generate bitstream. (xtp244 slide 42)

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 3 out of 119 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: init_calib_complete, sys_rst, and tg_compare_error.

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 3 out of 119 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: init_calib_complete, sys_rst, and tg_compare_error.

 
 

mig_example_failed_2017_4_2.png

But have noticed that after TCL command set_property -dict [list CONFIG.C_PROBE_IN0_WIDTH {4}] [get_ips vio_0] return a 0, it did not have the update_compile_order -fileset sources_1 follow it. Have done with VIO 3.0(rev10 and rev17 after update), but it is still having same error.

Problem ports: init_calib_complete, sys_rst, and tg_compare_error but i cannot set these 3 pins in the MIG wizard since the drop down list do not have Bank34.The xtp244-zc706-mig-c-2015-4.pdf also did not mention that these 3 pins need to be set.

 

mig_example_ddr3_signals.png

Also i have repeated the same example on vivado2015.4 and it is showing the same errors with an additional issue on the MIG wizard,

when setting DDR3 pinouts, clicked on the “Read xdc/ucf” or “Save pinouts” button, MIG crashed. Have to manually input all pins to bypass this but time consuming. 

mig_example_failed_2015_4_1.png

mig_example_ui_failed_2015_4_1.png

Do the 3 pins have to be set?

Are there any steps or settings that is not mention but needs to be done?

Is there another PL-DDR3 vivado example code for zc706?

 

thanks,

benjamin tan

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yunusbaskan
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Registered: ‎11-25-2019

Hello @xlxuserc,

I have two ideas about the problem that you encountered:

1) You can connect these pins to leds and switch (init_complete and tg_error to leds and rst signal to a switch) if your board has.

2) In your top module, you can convert sys_rst, init_complete and tg_error ports to signals and you can give sys_rst as '1' (because sys_rst is active-low signal.).

In the configuration setting page, if you connect these three signals to some ports, MIG handles xdc (porting) inside. However, if you choose "no connect", it means that you want to connect these signals to ports or signals that you want to.

I hope I could understand your problem and help you. Good luck.

Regards,

Yunus.

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yunusbaskan
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Registered: ‎11-25-2019

Hello @xlxuserc,

I have two ideas about the problem that you encountered:

1) You can connect these pins to leds and switch (init_complete and tg_error to leds and rst signal to a switch) if your board has.

2) In your top module, you can convert sys_rst, init_complete and tg_error ports to signals and you can give sys_rst as '1' (because sys_rst is active-low signal.).

In the configuration setting page, if you connect these three signals to some ports, MIG handles xdc (porting) inside. However, if you choose "no connect", it means that you want to connect these signals to ports or signals that you want to.

I hope I could understand your problem and help you. Good luck.

Regards,

Yunus.

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rpr
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Registered: ‎11-09-2017

Hi @xlxuserc 

You haven't assign pin locations to sys_rest, init_cal, and tg_compare.

Assign, Else add below constraints.

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

refer to https://www.xilinx.com/support/answers/56354.html

 

Regards
Pratap

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xlxuserc
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Registered: ‎08-25-2020

Dear Pratap, Yunus,

Thanks for all your replies.

The evaluation kit i using is the Xilinx zc706, EK-Z7-ZC706-G. The MIG example tutorial xtp244 is exactly for this zc706 board so expectation is everything should work as per the document steps. The xtp244 pg28 did not mention any need to set for these 3 pins. The default in MIG is “no connect” for all 3 pins.

xlxuserc_0-1606277829633.png

 

From Vivado2017.4 implementation design, it is showing the 3 pins number as sys_rst(pin AE20), init_calib_complete(pin V21) tg_error(pin W24)

xlxuserc_1-1606277829640.png

 

Based on zc706 evaluation kit schematic(zc706-schematic-xtp215-rev1-1.pdf), these 3 pins is connected to for REC_CLOCK_C_N(AE20), HDMI_R_D34(V21), FMC_HPC_LA17_CC_N(W24), they are not used for the SODIMM.  The AE20 is used as output pin already on zc706 but Vivado need input for sys_rst.

MIG wizard drop down list do not have bank9 AE20 and bank13 V21 for me to select. How to assign sys_rst(pin AE20), init_calib_complete(pin V21) to the correct pinouts as in the schematic or leave them as default “no connect” is correct??

xlxuserc_2-1606277829685.png

 

xlxuserc_3-1606277829706.png

 

As for the below 2 tcl commands, the error message stated that this is not recommended. So will this damage the xc7z045 SoC or the HDMI IC, SI5324C on the zc706 evalutaion kit when program to it? Can you confirm this is safe to do it?

Also, can you show me or provide links to the correct way and correct setting for these 3 pins for Xilinx evaluation kit zc706 so to generate bitstream?

Are there missing steps in Xilinx MIG example xtp244-zc706-mig-c-2015-4.pdf tutorial to generate bitstream?

 

thanks,

benjamin

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xlxuserc
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Registered: ‎08-25-2020

Dear all,

Have tried the 2 commands in tcl and got the message "save_constraints -force". then have re-run synthesis, implementation and generate bitstream.

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

but the issue remains and generate bitstream still failed for this MIG example.

 

thanks,

benjamin

 

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xlxuserc
Observer
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Registered: ‎08-25-2020

Dear Yunus,

Thanks for your reply.

Have checked again the zc706 board and found that 7z045 SoC has pins connected to 4 LEDs and 3 switches.

Have tried assigning the pins as per your suggestion1),  to 2 LEDs and 1 switch.

pin assignments as below:

sys_rst(bank11, pin AK25), switch

init_calib_complete(bank11, W21), LED

tg_error(bank11, pin Y21), LED

 

xlxuserc_0-1608003239569.png

 

and run implementation is ok without the error and now able to generate bitstream. The MIG example can run on zc706 board with generate bitstream.

xlxuserc_1-1608003275499.png

is "no connect" option setting simply means that signals are not brought out to a pin ?

thanks,

benjamin

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yunusbaskan
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Registered: ‎11-25-2019

Hi @xlxuserc,

It is exactly what you said!

 

Yunus

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